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參數(shù)資料
型號： ATMEGA329V-8MUR
廠商： Atmel
文件頁數(shù)： 96/146頁
文件大?。?/td> 0K
描述： MCU AVR 32K FLASH 8MHZ 64QFN
產(chǎn)品培訓模塊： megaAVR Introduction
標準包裝： 4,000
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： SPI，UART/USART，USI
外圍設備： 欠壓檢測/復位，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 54
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-VFQFN 裸露焊盤
包裝： 帶卷 (TR)
其它名稱： ATMEGA329V-8MUR-ND
ATMEGA329V-8MURTR
2010-2012 Microchip Technology Inc.
DS41440C-page 337
PIC16(L)F1825/1829
29.2
Instruction Descriptions
ADDFSR
Add Literal to FSRn
Syntax:
[ label ] ADDFSR FSRn, k
Operands:
-32
k 31
n
[ 0, 1]
Operation:
FSR(n) + k
FSR(n)
Status Affected:
None
Description:
The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
FSRn is limited to the range 0000h -
FFFFh. Moving beyond these bounds
will cause the FSR to wrap around.
ADDLW
Add literal and W
Syntax:
[ label ] ADDLW
k
Operands:
0
k 255
Operation:
(W) + k
(W)
Status Affected:
C, DC, Z
Description:
The contents of the W register are
added to the eight-bit literal ‘k’ and the
result is placed in the W register.
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
f,d
Operands:
0
f 127
d
0,1
Operation:
(W) + (f)
(destination)
Status Affected:
C, DC, Z
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
ADDWFC
ADD W and CARRY bit to f
Syntax:
[ label ] ADDWFC
f {,d}
Operands:
0
f 127
d
[0,1]
Operation:
(W) + (f) + (C)
dest
Status Affected:
C, DC, Z
Description:
Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
ANDLW
AND literal with W
Syntax:
[ label ] ANDLW
k
Operands:
0
k 255
Operation:
(W) .AND. (k)
(W)
Status Affected:
Z
Description:
The contents of W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W register.
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
f,d
Operands:
0
f 127
d
0,1
Operation:
(W) .AND. (f)
(destination)
Status Affected:
Z
Description:
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ASRF
Arithmetic Right Shift
Syntax:
[ label ] ASRF
f {,d}
Operands:
0
f 127
d
[0,1]
Operation:
(f<7>)
dest<7>
(f<7:1>)
dest<6:0>,
(f<0>)
C,
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in reg-
ister ‘f’.
register f
C
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