參數(shù)資料
型號： ATMEGA329V-8MUR
廠商： Atmel
文件頁數(shù)： 56/146頁
文件大?。?/td> 0K
描述： MCU AVR 32K FLASH 8MHZ 64QFN
產(chǎn)品培訓模塊： megaAVR Introduction
標準包裝： 4,000
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： SPI，UART/USART，USI
外圍設(shè)備： 欠壓檢測/復位，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 54
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-VFQFN 裸露焊盤
包裝： 帶卷 (TR)
其它名稱： ATMEGA329V-8MUR-ND
ATMEGA329V-8MURTR
PIC16(L)F1825/1829
DS41440C-page 300
2010-2012 Microchip Technology Inc.
26.1.2.8
Asynchronous Reception Setup:
1.
Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 26.3 “EUSART
2.
Clear the ANSEL bit for the RX pin (if applicable).
3.
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5.
If 9-bit reception is desired, set the RX9 bit.
6.
Enable reception by setting the CREN bit.
7.
The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
8.
Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
9.
Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
26.1.2.9
9-bit Address Detection Mode Setup
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 26.3 “EUSART
2.
Clear the ANSEL bit for the RX pin (if applicable).
3.
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5.
Enable 9-bit reception by setting the RX9 bit.
6.
Enable address detection by setting the ADDEN
bit.
7.
Enable reception by setting the CREN bit.
8.
The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
9.
Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 26-5:
ASYNCHRONOUS RECEPTION
Start
bit
bit 7/8
bit 1
bit 0
bit 7/8
bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8 Stop
bit
RX/DT pin
Reg
Rcv Buffer Reg.
Rcv Shift
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
RCIDL
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