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參數資料
| 型號： | ATMEGA329V-8MUR |
| 廠商： | Atmel |
| 文件頁數： | 34/146頁 |
| 文件大小： | 0K |
| 描述： | MCU AVR 32K FLASH 8MHZ 64QFN |
| 產品培訓模塊： | megaAVR Introduction |
| 標準包裝： | 4,000 |
| 系列： | AVR® ATmega |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 8MHz |
| 連通性： | SPI，UART/USART，USI |
| 外圍設備： | 欠壓檢測/復位，LCD，POR，PWM，WDT |
| 輸入/輸出數： | 54 |
| 程序存儲器容量： | 32KB（16K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 1K x 8 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 5.5 V |
| 數據轉換器： | A/D 8x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | ATMEGA329V-8MUR-ND ATMEGA329V-8MURTR |
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2010-2012 Microchip Technology Inc.
DS41440C-page 281
PIC16(L)F1825/1829
25.6.10
SLEEP OPERATION
While in Sleep mode, the I2C slave module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSPx interrupt is enabled).
25.6.11
EFFECTS OF A RESET
A Reset disables the MSSPx module and terminates
the current transfer.
25.6.12
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSPx module is disabled. Control of the I2C bus may
be taken when the P bit of the SSPxSTAT register is
set, or the bus is Idle, with both the S and P bits clear.
When the bus is busy, enabling the SSPx interrupt will
generate the interrupt when the Stop condition occurs.
In multi-master operation, the SDAx line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLxIF bit.
The states where arbitration can be lost are:
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
25.6.13
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus
arbitration. When the master outputs address/data bits
onto the SDAx pin, arbitration takes place when the
master outputs a ‘1’ on SDAx, by letting SDAx float high
and another master asserts a ‘0’. When the SCLx pin
floats high, data should be stable. If the expected data
on SDAx is a ‘1’ and the data sampled on the SDAx pin
is ‘0’, then a bus collision has taken place. The master
will set the Bus Collision Interrupt Flag, BCLxIF and
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDAx and SCLx lines are deasserted and
the SSPxBUF can be written to. When the user services
the bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDAx and SCLx
lines are deasserted and the respective control bits in
the SSPxCON2 register are cleared. When the user
services the bus collision Interrupt Service Routine and
if the I2C bus is free, the user can resume communica-
tion by asserting a Start condition.
The master will continue to monitor the SDAx and SCLx
pins. If a Stop condition occurs, the SSPxIF bit will be set.
A write to the SSPxBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPxSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 25-32:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDAx
SCLx
BCLxIF
SDAx released
SDAx line pulled low
by another source
Sample SDAx. While SCLx is high,
data does not match what is driven
Bus collision has occurred.
Set bus collision
interrupt (BCLxIF)
by the master.
by master
Data changes
while SCLx = 0
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