參數(shù)資料
型號： ATMEGA329V-8MUR
廠商： Atmel
文件頁數(shù)： 127/146頁
文件大?。?/td> 0K
描述： MCU AVR 32K FLASH 8MHZ 64QFN
產(chǎn)品培訓(xùn)模塊： megaAVR Introduction
標(biāo)準(zhǔn)包裝： 4,000
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： SPI，UART/USART，USI
外圍設(shè)備： 欠壓檢測/復(fù)位，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 54
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-VFQFN 裸露焊盤
包裝： 帶卷 (TR)
其它名稱： ATMEGA329V-8MUR-ND
ATMEGA329V-8MURTR
55
2552K–AVR–04/11
ATmega329/3290/649/6490
12.2
Register Description
12.2.1
EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in Table 12-1. The value on the INT0 pin is sampled before detecting
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
12.2.2
External Interrupt Mask Register – EIMSK
Bit 7 – PCIE3: Pin Change Interrupt Enable 3
When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 3 is enabled. Any change on any enabled PCINT30..24 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT3
Interrupt Vector. PCINT30..24 pins are enabled individually by the PCMSK3 Register.
This bit is reserved bit in ATmega329/649 and should always be written to zero.
Bit 6 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT2
Interrupt Vector. PCINT23..16 pins are enabled individually by the PCMSK2 Register.
This bit is reserved bit in ATmega329/649 and should always be written to zero.
Bit
765
4321
0
–
ISC01
ISC00
EICRA
Read/Write
R
RRRR
R
R/W
Initial Value
000
0000
0
Table 12-1.
Interrupt 0 Sense Control
ISC01
ISC00
Description
0
The low level of INT0 generates an interrupt request.
0
1
Any logical change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
Bit
7
654
32
10
PCIE3
PCIE2
PCIE1
PCIE0
–
–INT0
EIMSK
Read/Write
R/W
R
R/W
Initial Value
0
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