參數(shù)資料
型號： ATMEGA329V-8MUR
廠商： Atmel
文件頁數(shù)： 61/146頁
文件大?。?/td> 0K
描述： MCU AVR 32K FLASH 8MHZ 64QFN
產(chǎn)品培訓(xùn)模塊： megaAVR Introduction
標(biāo)準(zhǔn)包裝： 4,000
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： SPI，UART/USART，USI
外圍設(shè)備： 欠壓檢測/復(fù)位，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 54
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-VFQFN 裸露焊盤
包裝： 帶卷 (TR)
其它名稱： ATMEGA329V-8MUR-ND
ATMEGA329V-8MURTR
2010-2012 Microchip Technology Inc.
DS41440C-page 305
PIC16(L)F1825/1829
26.3
EUSART Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCON register selects 16-bit
mode.
The SPBRGH, SPBRGL register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCON register. In
Synchronous mode, the BRGH bit is ignored.
Table 26-3 contains the formulas for determining the
baud rate. Example 26-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 26-3. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGH, SPBRGL register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
EXAMPLE 26-1:
CALCULATING BAUD
RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
Solving for SPBRGH:SPBRGL:
X
FOSC
Desired Baud Rate
---------------------------------------------
64
--------------------------------------------- 1
–
=
Desired Baud Rate
FOSC
64 [SPBRGH:SPBRGL]
1
+
------------------------------------------------------------------------
=
16000000
9600
------------------------
64
------------------------1
–
=
25.042
25
==
Calculated Baud Rate
16000000
64 25
1
+
---------------------------
=
9615
=
Error
Calc. Baud Rate Desired Baud Rate
–
Desired Baud Rate
--------------------------------------------------------------------------------------------
=
9615 9600
–
9600
----------------------------------
0.16%
==
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