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參數(shù)資料
型號： ATMEGA329V-8MUR
廠商： Atmel
文件頁數(shù)： 26/146頁
文件大小： 0K
描述： MCU AVR 32K FLASH 8MHZ 64QFN
產(chǎn)品培訓模塊： megaAVR Introduction
標準包裝： 4,000
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： SPI，UART/USART，USI
外圍設(shè)備： 欠壓檢測/復位，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 54
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-VFQFN 裸露焊盤
包裝： 帶卷 (TR)
其它名稱： ATMEGA329V-8MUR-ND
ATMEGA329V-8MURTR
PIC16(L)F1825/1829
DS41440C-page 274
2010-2012 Microchip Technology Inc.
25.6.4
I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition (Figure 25-26), the user
sets the Start Enable bit, SEN bit of the SSPxCON2
register. If the SDAx and SCLx pins are sampled high,
the Baud Rate Generator is reloaded with the contents
of SSPxADD<7:0> and starts its count. If SCLx and
SDAx are both sampled high when the Baud Rate
Generator times out (TBRG), the SDAx pin is driven
low. The action of the SDAx being driven low while
SCLx is high is the Start condition and causes the S bit
of the SSPxSTAT1 register to be set. Following this,
the Baud Rate Generator is reloaded with the contents
of SSPxADD<7:0> and resumes its count. When the
Baud Rate Generator times out (TBRG), the SEN bit of
the SSPxCON2 register will be automatically cleared
by hardware; the Baud Rate Generator is suspended,
leaving the SDAx line held low and the Start condition
is complete.
FIGURE 25-26:
FIRST START BIT TIMING
Note 1:
If at the beginning of the Start condition,
the SDAx and SCLx pins are already
sampled low, or if during the Start
condition, the SCLx line is sampled low
before the SDAx line is driven low, a bus
collision
occurs,
the
Bus
Collision
Interrupt Flag, BCLxIF, is set, the Start
condition is aborted and the I2C module is
reset into its Idle state.
2:
The Philips I2C Specification states that
a bus collision cannot occur on a Start.
SDAx
SCLx
S
TBRG
1st bit
2nd bit
TBRG
SDAx = 1,
At completion of Start bit,
SCLx = 1
Write to SSPxBUF occurs here
TBRG
hardware clears SEN bit
TBRG
Write to SEN bit occurs here
Set S bit (SSPxSTAT<3>)
and sets SSPxIF bit
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