[ label ] DECFSZ f,d Operands: " />
參數(shù)資料
型號： ATMEGA329V-8MUR
廠商： Atmel
文件頁數(shù)： 100/146頁
文件大小： 0K
描述： MCU AVR 32K FLASH 8MHZ 64QFN
產品培訓模塊： megaAVR Introduction
標準包裝： 4,000
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： SPI，UART/USART，USI
外圍設備： 欠壓檢測/復位，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 54
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 8x10b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-VFQFN 裸露焊盤
包裝： 帶卷 (TR)
其它名稱： ATMEGA329V-8MUR-ND
ATMEGA329V-8MURTR
PIC16(L)F1825/1829
DS41440C-page 340
2010-2012 Microchip Technology Inc.
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Operands:
0
f 127
d
[0,1]
Operation:
(f) - 1
(destination);
skip if result = 0
Status Affected:
None
Description:
The contents of register ‘f’ are decre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a
NOP is executed instead, making it a
2-cycle instruction.
GOTO
Unconditional Branch
Syntax:
[ label ]
GOTO k
Operands:
0
k 2047
Operation:
k
PC<10:0>
PCLATH<6:3>
PC<14:11>
Status Affected:
None
Description:
GOTO is an unconditional branch. The
eleven-bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two-cycle instruction.
INCF
Increment f
Syntax:
[ label ]
INCF f,d
Operands:
0
f 127
d
[0,1]
Operation:
(f) + 1
(destination)
Status Affected:
Z
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the
result is placed back in register ‘f’.
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ]
INCFSZ f,d
Operands:
0
f 127
d
[0,1]
Operation:
(f) + 1
(destination),
skip if result = 0
Status Affected:
None
Description:
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, a NOP is
executed instead, making it a 2-cycle
instruction.
IORLW
Inclusive OR literal with W
Syntax:
[ label ]
IORLW k
Operands:
0
k 255
Operation:
(W) .OR. k
(W)
Status Affected:
Z
Description:
The contents of the W register are
OR’ed with the eight-bit literal ‘k’. The
result is placed in the W register.
IORWF
Inclusive OR W with f
Syntax:
[ label ]
IORWF
f,d
Operands:
0
f 127
d
[0,1]
Operation:
(W) .OR. (f)
(destination)
Status Affected:
Z
Description:
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the
result is placed back in register ‘f’.
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