參數(shù)資料
型號(hào)： AM79C864AKCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Physical Layer Controller With Scrambler (PLC-S)
中文描述： 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP120
封裝： PLASTIC, QFP-120
文件頁(yè)數(shù)： 29/51頁(yè)
文件大?。?/td> 271K
代理商： AM79C864AKCW
AMD
P R E L I M I N A R Y
3-31
Am79C864A
NP
ERR
Addr
(Hex)
17
LSDO
IE
CTR
MINI
CTR
VSYM
CTR
PHYINV
EBUF
ERR
TNE
EXPIRED
TPC
EXPIRED
PCM
ENABLED
PCM
BREAK
SELF
TEST
TRACE
PROP
PCM
CODE
LS
MATCH
PARITY
ERR
INTR-EVENT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15535B-12
Table 10. INTR_EVENT Register
Bit
Name
Definition
15
NP_ERR
An event indicating that the Node Processor has requested a read or write to an invalid
register. This case includes a write to a read-only register (such as this one), a read of
a write-only register, a write to a XMIT_VECTOR or VECTOR_LENGTH register when
PCM_SIGNALLING is set, a write to the TPC Timer register while the PCM is not in the
MAINT state, and a write to the TNE Timer register while the PCM is not in the MAINT
state or NOISE_TIMER is set.
14
LSDO
This bit is set whenever SD0 pin is asserted.
13
LE_CTR
An event indicating that the Link Error Event Counter has reached the value contained
in the LE_THRESHOLD register.
12
MINI_CTR
Indicates that either of two events has occurred in the MIN_IDLE_CTR: the Idle
Counter Minimum Detector has changed to a lower value; or, the Minimum Idle Gap
Counter has incremented or overflowed, depending on the MINI_CTR_INTRS bit in
the PLC_CNTRL_A register.
11
VSYM_CTR
An event indicating that a Violation Symbol Counter has incremented or overflowed,
depending on the VSYM_CTR_INTRS bit in the PLC_CNTRL_A register.
10
PHYINV
An event indicating that the Physical Layer Invalid signal has been asserted.
09
EBUF_ERR
An event indicating that the Elasticity Buffer has detected an overflow or underflow.
08
TNE_EXPIRED
An event indicating that the TNE Timer has expired, i.e. reached zero.
07
TPC_EXPIRED
An event indicating that the TPC Timer has expired, i.e. reached zero.
06
PCM_ENABLED
An event indicating the PCM has asserted SC_JOIN, has completed scrubbing, and is
in the ACTIVE state.
05
PCM_BREAK
An event indicating the PCM has entered the BREAK state.
04
SELF_TEST
An event indicating Quiet or Halt Line State has been received while the PCM is in the
TRACE state.
03
TRACE_PROP
An event indicating that Master Line State has been received while the PCM is in the
ACTIVE or TRACE state.
02
PCM_CODE
An event indicating the PCM has completed transmitting the last bit in the vector
written to the XMIT_VECTOR register and has received the corresponding bit of the
RCV_VECTOR, or that the Link Confidence Test has completed. In the case where
signalling has completed, PCM_CODE will not be set until the RCF flag has been set
again.
01
LS_MATCH
An event indicating that the line state detected equals the line state in the MATCH_LS
field of the PLC_CNTRL_B register.
00
PARITY_ERR
An event indicating that a parity error has been detected on the TX 9–0 input pins.
This bit will not be set if ENA_PAR_CHK bit in PLC_CNTRL_A register is cleared.
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