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| 型號： | AM79C864AKCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Physical Layer Controller With Scrambler (PLC-S) |
| 中文描述： | 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁數(shù)： | 10/51頁 |
| 文件大小： | 271K |
| 代理商： | AM79C864AKCW |
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AMD
P R E L I M I N A R Y
3-12
The SUPERNET 2 Family for FDDI 1994 Data Book
PIN DESCRIPTION
Clock Signals
BCLK
Byte Clock (Input)
BCLK is a 12.5 MHz clock. It is used by the PLC-S to
clock most internal operations, clock RX 9–0 to the MAC
device and, along with LSCLK, latch TX 9–0 from the
MAC device.
NPCLK
Node Processor Clock (Input)
NPCLK is used to latch Node Processor inputs, run the
Node Processor Interface state machine, and clock out-
put signals to the Node Processor. It is distinct from the
BCLK for test and diagnostic purposes only. For normal
operations, the BCLK and NPCLK pins MUST be tied
together.
RSCLK
Recovered Symbol Clock (Input)
RSCLK is a 25 MHz clock. It is recovered from the data
sent to the Physical Data Receiver (PDR) by the up-
stream station in the ring. It is used to latch RDAT 4–0
from the PDR device. It is also used for clocking the
Framer and the Elasticity Buffer input controller.
LSCLK
Local Symbol Clock (Input)
LSCLK is a 25 MHz clock. It is used by the PLC-S to
clock TDAT 4–0 to the Physical Data Transmitter (PDT)
and, along with BCLK, to latch TX 9–0 from the MAC
device.
Receive Data Signals
RX 9–0
Receive Data Bus (Output)
RX 9–0 is a ten bit output bus used to transfer symbol
pairs from the PLC-S to a MAC device, or to another
PLC-S. The ten bits are clocked to the MAC device on
the rising edge of BCLK. RX 9–5 contain the most sig-
nificant symbol and RX 4–0 contain the least significant
symbol of the framed byte. Bit 9 is the upper control bit
and bit 4 is the lower control bit.
RXPAR
Receive Data Parity bit (Output)
RXPAR is an output signal used to enhance error detec-
tion on the RX bus. If there is an odd number of ones on
RX 9–0 then RXPAR will be one, and if there is an even
number of ones on RX 9–0 then RXPAR will be zero
(even parity). When the PLC-S is in Bypass mode (that
is when the data output on RX 9–0 is the data input on
TX 9–0) RXPAR is not calculated and is just the value
input on TXPAR.
RDAT 4–0
Receive Data Bus (Input)
RDAT 4–0 is a five bit input bus used to transfer data
from the PDR device to the PLC-S. Data is latched by
the PLC-S on the rising edge of RSCLK.
Transmit Data Signals
TDAT 4–0
Physical Transmit Data Bus (Output)
TDAT 4–0 is a five bit output bus used to transfer sym-
bols from the PLC-S to the PDT. The symbols are
clocked to the PDT on the rising edge of LSCLK.
TX 9–0
Transmit Data Bus (Input)
TX 9–0 is a ten bit input bus used to transfer symbol
pairs from a MAC device, or from another PLC-S, to the
PLC-S. The ten bits are latched by the PLC-S on the fall-
ing edge of LSCLK. Bits 9–5 of the bus contain the first
symbol to be transmitted on the fiber and bits 4–0 con-
tain the second symbol. Bit 9 is the upper control bit and
bit 4 is the lower control bit.
TXPAR
Transmit Data Parity bit (Input)
TXPAR is an input signal used to implement even parity
on the TX bus. If there is an odd number of ones on
TX9–0 then TXPAR should be one and if there is an
even number of ones on TX 9–0 then TXPAR should be
zero.
Node Processor Interface Signals
INT
Interrupt (Output, Active Low)
The
INT
signal indicates an interrupt request from the
PLC-S. This signal is active until cleared by reading the
INTR_EVENT register at address 17 (hex).
CS
Chip Select (Input, Active Low)
CS
selects the PLC-S for the current bus cycle.
NPADDR 4–0
Node Processor Address Bus (Input)
The NPADDR 4–0 bus is a five bit input bus used to se-
lect one of the registers in the PLC-S for a read or write
cycle.
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