參數(shù)資料
型號(hào)： AM79C864AKCW
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： Physical Layer Controller With Scrambler (PLC-S)
中文描述： 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP120
封裝： PLASTIC, QFP-120
文件頁(yè)數(shù)： 22/51頁(yè)
文件大?。?/td> 271K
代理商： AM79C864AKCW
AMD
P R E L I M I N A R Y
3-24
The SUPERNET 2 Family for FDDI 1994 Data Book
PLC-S Status Register A (PLC_STATUS_A)
PLC_STATUS_A has address 10 (hex). It is read-only.
It is used to report status information to the Node Proc-
essor about the Line State Machine (LSM).
The PLC_STATUS_A register bit assignments are
listed in Table 5.
SYM
PR
CTR
10
SIGNAL
DETECT
PREV
LINE
ST
PREV
LINE
ST
LINE
ST
LINE
ST
LINE
ST
LSM
STATE
UNKN
LINE
ST
SYM
PR
CTR
SYM
PR
CTR
PLC_STATUS_A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Addr
(Hex)
15535B-10
REVISION_ID
Table 5. PLC_STATUS_A
Bit
Name
Definition
15–11
REVISION_ID
These bits give the revision identification. For Am79864A (PLC-S), these bits equal ‘11111’.
For Am79C864 (PLC), these bits equal ‘00000’.
10
SIGNAL_DETECT
This bit, when set, indicates that signal detect is deasserted. If SDO equals zero, then
SIGNAL_DETECT is one; if SDO equals one, then SIGNAL_DETECT is zero.
09–08
PREV_LINE_ST
This field contains the value of the previous line state whenever line state changes
from Quiet Line State, Master Line State, Halt Line State or Idle Line State (ILS16,
where ILS16 is achieved after 16 idle symbols) to another line state. When the line
state changes from anything else, this field will not be updated. It is further defined as
follows:
PREV_LINE_ST
00
01
10
11
This field contains the most recently recognized Line State by the LSM. LINE_ST is
further defined as follows:
Description
Quiet Line State (QLS)
Master Line State (MLS)
Halt Line State (HLS)
Idle Line State (ILS16 – achieved after 16 Idle symbols)
07–05
LINE_ST
LINE_ST
000
001
010
011
100
101
110
111
This field contains the state bit of the LSM state machine.
Description
Noise Line State (NLS)
Active Line State (ALS)
Undefined
Idle Line State (ILS4 – achieved after 4 Idle symbols)
Quiet Line State (QLS)
Master Line State (MLS)
Halt Line State (HLS)
Idle Line State (ILS16 – achieved after 16 Idle symbols)
04
LSM_STATE
03
UNKN_LINE_ST
This bit is the Unknown Line State Bit from the LSM. Since a minimum of sixteen
symbols is required to satisfy the entry conditions of a line state (four symbols in the
case of Idle Line State), the LSM uses this bit to indicate it is attempting to recognize a
new line state. This bit is set to a one when the line state is unknown and reset to a zero
when known.
02–00 SYM_PR_CTR
This field contains the LSM Symbol Pair Counter. When the count reaches seven,
indicating eight consecutive like symbol pairs, then Current Line State is set with the
new line state and the Unknown Line State Bit is reset. Note that Idle Line State (ILS4)
is reached after just two Idle symbol pairs.
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