參數(shù)資料
型號： AM79C864AKCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Physical Layer Controller With Scrambler (PLC-S)
中文描述： 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP120
封裝： PLASTIC, QFP-120
文件頁數(shù)： 21/51頁
文件大小： 271K
代理商： AM79C864AKCW
AMD
P R E L I M I N A R Y
3-23
Am79C864A
PLC-S Control Register C (PLC_CNTRL_C)
PLC_CNTRL_C has address OA (hex). It is readable
and writeable. Bits 1 through 15 are cleared with the as-
sertion of
RST
. Bit 0 (CIPHER_ENABLE) assumes the
same value as SCRM after
RST
is asserted.
The PLC_CNTRL_C register bit assignments are listed
in Table 4.
FOTOFF_
CTRL
RESERVED
SDOFF_
TIMER
SDOFF_
TIMER
SDON_
TIMER
SDON_
TIMER
FOTOFF_
CTRL
PLC_CNTRL_C
15
14
13
12
11
10
9
8
15535B-8
7
6
5
4
3
2
1
0
CIPHER_
ENABLE
SDON_
ENABLE
SDOFF_
ENABLE
RESERVED
CIPHER_
LPBCK
Addr
(Hex)
0A
Table 4. PLC_CNTRL_C
Bit
Name
Definition
15–14
RESERVED
These two bits are reserved for diagnostic purposes and must be 0 for normal operation.
13–12
SDOFF_TIMER
These two bits are used to select the timing values shown for deasserting Signal_Detect
ENABLE bit is set and scrambler/descrambler is enabled either (by SCRM or CIPHER_
ENABLE)
00=0.76
μ
s
01=1.32
μ
s
10=2.52
μ
s
11=5.12
μ
s
These two bits are used to select the timing values shown for asserting Signal_Detect if SDON_
ENABLE bit is set and scrambler/descrambler is enabled either by hardware or software.
11–10
SDON_TIMER
00=0.84
μ
s
01=1.32
μ
s
10=2.52
μ
s
11=5.12
μ
s
These two bits are used to control the assertion of FOTOFF signal of PLC-S if scrambler/
descrambler is enabled either (by SCRM or CIPHER_ENABLE). The following timing delays
are with respect to the time from which PLC-S output scrambled Quiet symbols on TDAT lines.
9–8
FOTOFF _CTRL
00=Timer is bypassed (i.e., FOTOFF is asserted at the same time when scrambled Quiet
symbols are output on TDAT lines)
01=30
μ
s delay
10=50
μ
s delay
11=FOTOFF is never asserted
If this bit is set and scrambler/descrambler is enabled (by SCRM or CIPHER_ENABLE), then
SDON_TIMER bits (11–10) will determine the delay for asserting the Signal_Detect signal.
During this time, the descrambler is allowed to acquire synchronization of its input stream.
7
SDON_ENABLE
6
SDOFF_ENABLE
If this bit is set and scrambler/descrambler is enabled (bySCRM or CIPHER_ENABLE ), then
SDOFF_TIMER bits (13–12) will determine the delay for deasserting the Signal_Detect signal.
5–2
RESERVED
Bits 5–2 are reserved and should be set to 0.
1
CIPHER_LPBCK
If this bit is set, then the output of the scrambler is looped back to the input of the
descrambler (within PLC-S).
0
CIPHER_ENABLE
This bit is used to enable and disable the scrambler/descrambler function if SCRM (pin #41)
is not asserted. If SCRM is asserted, this bit is automatically set to 1. If SCRM is not
asserted, the value of this bit is determined by software. The default state (SCRM not
asserted) is 0.
相關PDF資料
PDF描述
AM79C873 NetPHY⑩ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support
AM79C873KCW NetPHY⑩ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support
AM79C874VI NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver
Am79C874 NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver
AM79C874VC NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver
相關代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C864KC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver
AM79C870KC/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver
AM79C871KC/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver
AM79C873 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:NetPHY⑩ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support
AM79C873KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:NetPHY⑩ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*