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參數(shù)資料
| 型號： | AM79C864AKCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Physical Layer Controller With Scrambler (PLC-S) |
| 中文描述： | 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁數(shù)： | 28/51頁 |
| 文件大?。?/td> | 271K |
| 代理商： | AM79C864AKCW |
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AMD
P R E L I M I N A R Y
3-30
The SUPERNET 2 Family for FDDI 1994 Data Book
Link Error Event Threshold Register
(LE_THRESHOLD)
The Link Error Event Threshold register has address 05
(hex). It is readable and writeable and is cleared on the
assertion of
RST
. Bits 7 through 0 of this register contain
a value that controls when the LE_CTR bit in the
INTR_EVENT register is set. Whenever the value in the
LINK_ERR_CTR reaches the value contained in this
register the LE_CTR bit will be set. Bits 15 through 8 are
ignored and will always be read as zeros.
Interrupt Registers
The PLC-S has two interrupt registers which correspond
bit-for-bit. One of the registers contains bits set by inter-
rupt events and the other a mask which enables or dis-
ables the assertion of the
INT
pin due to a corresponding
interrupt event.
Interrupt Event Register (INTR_EVENT)
The Interrupt Event Register (INTR_EVENT) has ad-
dress 17 (hex). It is read-only and is cleared whenever it
is read, as well as when
RST
is asserted. It is used by
the PLC-S to report events to the node processor. Indi-
vidual bits are set by the PLC-S for the particular event
occurrences. When an interrupt is generated (via the
INT
pin), the node processor should read this register to
identify the source(s) of the interrupt.
Note that while the RUN_BIST bit in the PLC_CNTRL_A
register is set, all interrupts are masked (prevented from
asserting the
INT
pin) except BIST_DONE. Since this is
the only interrupt that can occur in this situation,
BIST_DONE need not occupy a bit in the INTR_EVENT
register. The interrupt is cleared by clearing the
RUN_BIST bit in the PLC_CNTRL_A register.
The INTR_EVENT register bit assignments are listed in
Table 10.
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