參數(shù)資料
型號： AM79C864AKCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Physical Layer Controller With Scrambler (PLC-S)
中文描述： 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP120
封裝： PLASTIC, QFP-120
文件頁數(shù)： 18/51頁
文件大?。?/td> 271K
代理商： AM79C864AKCW
AMD
P R E L I M I N A R Y
3-20
The SUPERNET 2 Family for FDDI 1994 Data Book
PLC-S Control Register B (PLC_CNTRL_B)
PLC_CNTRL_B has address 01 (hex). It is readable and
writeable. All bits of this register are cleared with the as-
sertion of
RST
. PLC_CNTRL_B contains signals and re-
quests to direct the process of physical connection
management. It is also used to control the Line State
Match interrupt.
The PLC_CNTRL_B register bit assignments are listed
in Table 3.
CONFIG
CNTRL
01
MATCH
LS
MATCH
LS
MATCH
LS
MATCH
LS
MAINT
LS
MAINT
LS
MAINT
LS
CLASS
S
PC
LOOP
PC
LOOP
PC
JOIN
LONG
PC
MAINT
PCM
CNTRL
PCM
CNTRL
PLC_CNTRL_B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Addr
(Hex)
15535B-7
Table 3. PLC_CNTRL_B
Bit
Name
Definition
15
CONFIG_CNTRL
The CONFIG_CNTRL bit allows control over the Scrub, Bypass, and Remote
Loopback datapath MUXes while the PCM is in normal operation. If this bit is set, then
the REQ_SCRUB, SC_BYPASS, and SC_REM_LOOP bits in the PLC_CNTRL_A
register will have effect regardless of the state of the PCM. If this bit is not set then the
REQ_SCRUB, SC_BYPASS and SC_REM_LOOP bits will only have effect if the
PCM is in the MAINT state.
14–11
MATCH_LS
The MATCH_LS field specifies line states to be compared with the currently detected
line state (as defined by LINE_ST in the PLC_STATUS_A register). When a match
occurs, the LS_MATCH interrupt bit in the INTR_EVENT register is asserted. Each bit
of MATCH_LS corresponds to a line state. If more than one bit is set, the interrupt is
signalled if any of the line states match the current line state. If no bits are set, the
interrupt is signalled on any change in the LINE_ST field or the UNKN_LINE_ST bit. It
is defined as follows:
MATCH_LS
0000
1XXX
X1XX
XX1X
XXX1
In the above table, ”X” means don’t care. Also Idle Line State refers to ILS16, which is
signalled only after sixteen Idle symbols (eight Idle bytes) have been received.
Description
Interrupt on any change in LINE_ST or UNKN_LINE_ST
Interrupt on Quiet Line State
Interrupt on Master Line State
Interrupt on Halt Line State
Interrupt on Idle Line State
10–8
MAINT_LS
The MAINT_LS field defines the line state the PCM will source while in the MAINT
state. The PCM enters the MAINT state from the OFF state if the PC_MAINT bit is
asserted. It is further defined as follows:
MAINT_LS
000
001
010
011
100
101
110
Description
Transmit QUIET Line State
Transmit IDLE Line State
Transmit HALT Line State
Transmit MASTER Line State
Transmit QUIET Line State
Transmit QUIET Line State
Transmit PDR (Transmit PHY_DATA request)––the symbol
stream at TX 9–0 is transmitted
Transmit QUIET Line State
111
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