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| 型號： | AM79C864AKCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Physical Layer Controller With Scrambler (PLC-S) |
| 中文描述： | 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁數(shù)： | 16/51頁 |
| 文件大?。?/td> | 271K |
| 代理商： | AM79C864AKCW |
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AMD
P R E L I M I N A R Y
3-18
The SUPERNET 2 Family for FDDI 1994 Data Book
-
Addr
(Hex)
00
NOISE
TIMER
TNE-16
BIT
TPC-16
BIT
REQ-
SCRUB
VSYM-
-CTR-
INTRS
MINI-
CTR-
INTRS
LOOP
BACK
FOT-
OFF
EB-
LOC-
LOOP
LM-
LOC-
LOOP
SC-
BYPASS
SC-
REM-
LOOP
RF-
DISABLE
RUN-
BIST
PLC_CNTRL_A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15535B-6
ENA_
PAR_
CHK
Table 2. PLC_CNTRL_A
Bit
Name
Definition
15
Reserved
14
NOISE_TIMER
The NOISE_TIMER bit allows the noise timing function of the PCM to be used when
the PCM is in the MAINT state. This function causes the TNE Timer to be loaded with
the value in the NS_MAX register whenever the Line State Machine transitions from
Idle Line State to Noise Line State, Active Line State or Unknown Line State. If the
timer expires before Idle Line State is recognized, the TNE_EXPIRED bit in the
INTR_EVENT register is set.
13
TNE_16BIT
When TNE_16BIT is set it causes the TNE Timer to operate as a 16 bit timer. In this
mode the 2 bits of the TNE Clock Divider are bypassed and the TNE Timer is
incremented every 80 ns. TNE_16BIT can only be written if the PCM is in
the OFF or MAINT state.
12
TPC_16BIT
When TPC_16BIT is set it causes the TPC Timer to operate as a 16 bit timer. In this
mode the 8 bits of the TPC Clock Divider are bypassed and the TPC Timer is
incremented every 80 ns. TPC_16BIT can only be written if the PCM is in
the OFF or MAINT state.
11
REQ_SCRUB
The REQ_SCRUB bit allows limited access to the scrub capability of the PLC-S chip. If
the PCM is in the MAINT state or if the CONFIG_CNTRL bit in the PLC_CNTRL_B
register is set then the REQ_ SCRUB bit controls the Scrub MUX. If REQ_SCRUB is
set then Idle symbols are sourced at the RX 9–0 output port. The output at the
TDAT 4–0 output port is controlled separately by the MAINT_LS field in the
PLC_CNTRL_B register. This bit may be written at any time, but only takes effect
when the PCM is in the MAINT state or if the CONFIG_CNTRL bit in the
PLC_CNTRL_B register is set.
10
ENA_PAR_CHK
If this bit is set, then parity checking takes place on TX9–0 lines. If reset, then parity
checking is disabled.
Note: PLC-S supports even parity.
09
VSYM_CTR_INTRS
The VSYM_CTR_INTRS bit controls when the VSYM_CTR interrupt bit in the
INTR_EVENT register is asserted. When VSYM_CTR_INTRS is set, the interrupt is
generated only when the VIOL_SYM_CTR overflows (reaches 256). When
VSYM_CTR_INTRS is cleared, the interrupt is generated every time the
VIOL_SYM_CTR is incremented (whenever a violation symbol is detected).
08
MINI_CTR_INTRS
The MINI_CTR_INTRS bit partially controls when the MINI_CTR interrupt bit in the
INTR_EVENT register is asserted. When MINI_CTR_INTRS is set, the interrupt is
generated when the Minimum Idle Gap Counter portion of MIN_IDLE_CTR overflows
(reaches16). When MINI_CTR_INTRS is cleared, the interrupt is generated every time
the counter is incremented (whenever a minimum length Idle gap is detected). Note
that this bit does not affect interrupts caused by the Idle Counter Minimum Detector
portion of MIN_IDLE_CTR.
07
LOOPBACK
When LOOPBACK is set, it causes the
LPBCK
output pin to be asserted low. This, in
turn, causes data to be looped back from the output of the PDT chip to the input of the
PDR chip.
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