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參數(shù)資料
| 型號： | AK4683_07 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| 中文描述： | 異步多聲道音頻編解碼器署長/噸 |
| 文件頁數(shù)： | 69/84頁 |
| 文件大?。?/td> | 1077K |
| 代理商： | AK4683_07 |
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[AK4683]
MS0427-E-02
2007/04
- 69 -
Addr
05H
Register Name
Clock Select 4
Default
D7
0
0
D6
XTL1
0
D5
XTL0
0
D4
D3
D2
D1
D0
MSB
0
CKSDT
0
CKSB2
0
CKSB1
1
CKSB0
0
MSB: Master/Slave control for input data of PORTB.
Refer Table 17.
CKSB2-0: Clock control for PORTB.
Refer Table 14.
CKSDT: Clock control for DIT.
Refer Table 57.
XTL1-0: X’tal Frequency control
00: 11.2896MHz (default)
01: 12.288MHz
10: 24.576MHz
11: (channel status)
Register Name
Sampling Speed
Default
Addr
06H
D7
0
0
D6
D5
D4
D3
0
0
D2
D1
D0
ACKSAI
0
ACKSAO
0
ACKSB
0
DFSAD
0
DFSDA1
0
DFSDA0
0
DFSDA1-0: DAC sampling speed control
These settings are ignored in Auto Setting Mode. Refer Table 22.
DFSAD: ADC sampling speed control
This setting is ignored in Auto Setting Mode. Refer Table 21.
ACSKB: Auto Setting Mode of PORTB
0: Disable, Manual Setting Mode (default)
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKSB bit “1”. In this case, the setting of
DFSAD, DFSDA1-0 bits of the block connecting this PORT is ignored. When this bit is “0”,
DFSAD, DFSDA1-0 bits set the sampling speed mode.
ACSKAO: Auto Setting Mode of PORTA Output
0: Disable, Manual Setting Mode (default)
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKSAO bit “1”. In this case, the setting of
DFSAD, DFSDA1-0 bits of the block connecting this PORT is ignored. When this bit is “0”,
DFSAD, DFSDA1-0 bits set the sampling speed mode.
ACSKAI: Auto Setting Mode of PORTA Input
0: Disable, Manual Setting Mode (default)
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKSAI bit “1”. In this case, the setting of
DFSAD, DFSDA1-0 bits of the block connecting this PORT is ignored. When this bit is “0”,
DFSAD, DFSDA1-0 bits set the sampling speed mode.
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