參數(shù)資料
型號: AK4683_07
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: Asynchronous Multi-Channel Audio CODEC with DIR/T
中文描述: 異步多聲道音頻編解碼器署長/噸
文件頁數(shù): 50/84頁
文件大?。?/td> 1077K
代理商: AK4683_07
[AK4683]
MS0427-E-02
2007/04
- 50 -
Biphase Output
The AK4683 can output either the through output (from RX) or transmitter output (DIT) via TX pin. Those could be
selected by DIT bit. The source of the through output from TX0 could be selected among RX0-3 by OPS0, 1 bits. When
output DIT data, V bit could be controlled by VIN bit and first 5 bytes of C bit could be controlled by CT39-CT0 bits in
control registers. When bit0= “0”(consumer mode), bit20-23 (Audio channel) could not be controlled directly but be
controlled by CT20 bit. When the CT20 bit is “1”, the AK4683 outputs “1000” as C20-23 for left channel and outputs
“0100” at C20-23 for right channel automatically. When CT20 bit is “0”, the AK4683 outputs “0000” set as “1000” for
sub frame 1, and “0100” for sub frame 2. U bits are fixed to “0”.
DIT bit
OPS1 bit
OPS0 bit
0
0
0
0
0
1
0
1
0
0
1
1
1
*
*
Table 54. TX Source Control
CM1-0 bit, CLKDT bit, CKSDT bit and OCKS1-0 select the clock source of DIT. This clock must be the same clock as
the clock sources of PORT connecting to DIT.
CM1
CM0
UNLOCK
0
0
-
0
1
-
0
1
0
1
1
1
-
Table 55. Clock Mode Control
CLKDT bit
0
1
Table 56. EXTCLK Control
CKSDT
OCKS1
OCKS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Table 57. MCLKO Speed
TX Source
RX0
RX1
RX2
RX3
DIT
(default)
Clock Source
RMCK
EXTCLK
RMCK
EXTCLK
EXTCLK
(default)
Clock Source
XTI
MCLK2
EXTCLK
256fs
256fs
512fs
128fs
384fs
384fs
768fs
192fs
fs(max)
96kHz
96kHz
48kHz
192kHz
48kHz
48kHz
32kHz
96kHz
相關(guān)PDF資料
PDF描述
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