參數(shù)資料
型號: AK4683_07
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: Asynchronous Multi-Channel Audio CODEC with DIR/T
中文描述: 異步多聲道音頻編解碼器署長/噸
文件頁數(shù): 46/84頁
文件大?。?/td> 1077K
代理商: AK4683_07
[AK4683]
MS0427-E-02
2007/04
- 46 -
OPERATION OVERVIEW (DIR/DIT part)
192kHz Clock Recovery
On chip low jitter PLL has a wide lock range with 32kHz to 192kHz and the lock time is less than 20ms. The AK4683
has the sampling frequency detect function. By either the clock comparison against X’tal oscillator or using the channel
status, the AK4683 detects the sampling frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz).
The PLL loses lock when the received sync interval is incorrect.
Clock Operation Mode
When DIR is selected. the CM0/CM1 bits select the clock source and the data source of SDTO. In Mode 2, the clock
source is automatically switched from PLL to XTI/MCLK2 when PLL goes unlock state. In Mode 3, the clock source is
fixed to XTI/MCLK2, but PLL is also operating and the recovered data such as C bits can be monitored. For Mode 2
and 3, it is recommended that the frequency of XTI/MCLK2 is different from the recovered frequency from PLL.
Mode
CM1
CM0
UNLOCK
PLL
0
0
0
-
ON
1
0
1
-
OFF
0
ON
2
1
0
1
ON
3
1
1
-
ON
ON: Oscillation (Power-up), OFF: STOP (Power-down)
Table 45. Clock Operation Mode select
When 384fs of XTI/MCLK2 is supplied to DIR/DIT, CKSDT bit should be set to “1”.
CKSDT bit
Clock Speed
0
1
x 2/3
Table 46. XTI/MCLK2 speed
Clock source
PLL
EXTCLK
PLL
EXTCLK
EXTCLK
SDTO
RX
DIT source
RX
DIT source
DIT source
(default)
x 1
(default)
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