
[AK4671]
MS0666-E-00
2007/10
- 90 -
■
Headphone Output (LOUT2/ROUT2 pins)
Power supply voltage for the LOUT2/ROUT2 is supplied from the AVDD pin and centered on the 0.5 x AVDD (typ)
voltage. The load resistance is 16
Ω
(min). HPG3-0 bits control the output volume (
Table 70
).
When LOM2 bit = “1”, DAC output signal is output to LOUT2 and ROUT2 pins as (L+R) mono signal.
When LOOPM2 bit = “1”, the MIC-Amp signal is output to LOUT2 and ROUT2 pins as (L+R) mono signal.
HPG3-0
Attenuation
DH
CH
BH
AH
:
:
2H
1H
0H
Table 70. LOUT2/ROUT2 Output Volume
When the MUTEN bit is “0”, the common voltage of LOUT2/ROUT2 falls and the outputs (LOUT2 and ROUT2 pins)
change to “L” (VSS1). When the MUTEN bit is “1”, the common voltage rises to VCOM voltage. A capacitor between
the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant is in proportional to AVDD voltage
and the capacitor at MUTET pin.
[Example]: A capacitor between the MUTET pin and ground = 1.0
μ
F, AVDD=3.3V:
Rise/fall time constant:
τ
= 100ms(typ), 250ms(max)
Time until the common goes to VSS1 when MUTEN bit = “1”
“0”: 500ms(max)
When PMLO2, PMRO2, PMLO2S and PMRO2S bits are “0”, the LOUT2/ROUT2 is powered-down, and the outputs
(LOUT2 and ROUT2 pins) go to “L” (VSS1).
PMLO2 bit, PMRO2 bit,
PMLO2S bit, PMRO2S bit
(default)
+6dB
+3dB
0dB
3dB
:
:
27dB
30dB
MUTE
(1) (2)
(4)
(3)
MUTEN bit
LOUT2 pin,
ROUT2 pin
Figure 72. Power-up/Power-down Timing for LOUT2/ROUT2
(1)
LOUT2/ROUT2 power-up (PMLO2, PMRO2, PMLO2S, PMRO2S bit = “1”). The outputs are still VSS1.
(2)
LOUT2/ROUT2 common voltage rises up (MUTEN bit = “1”).
(3)
LOUT2/ROUT2 common voltage falls down (MUTEN bit = “0”).
(4)
LOUT2/ROUT2 power-down (PMLO2, PMRO2, PMLO2S, PMRO2S bit = “0”). The outputs are VSS1. If the power
supply is switched off or LOUT2/ROUT2 is powered-down before the common voltage goes to VSS1, some POP
noise occurs.