參數(shù)資料
型號: AK4671EG
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: Stereo CODEC with MIC/RCV/HP-AMP
中文描述: 立體聲編解碼器麥克風(fēng)/垃圾車/惠普腺苷
文件頁數(shù): 103/164頁
文件大?。?/td> 1792K
代理商: AK4671EG
[AK4671]
MS0666-E-00
2007/10
- 103 -
PCM I/F A & B Format
AK4671 supports dual PCM I/F (PCM I/F A & PCM I/F B) that supports 3 kind of I/F (16bit Linear, 8bit A-Law and 8bit
μ
-Law) independently (
Table 82
and
Table 83
).
Mode
LAWA1
LAWA0
0
0
0
1
0
1
2
1
0
3
1
1
Table 82. PCM I/F A Mode (N/A: Not available)
Mode
LAWB1
LAWB0
0
0
0
1
0
1
2
1
0
3
1
1
Table 83. PCM I/F B Mode (N/A: Not available)
Four types of data formats are available and are selected by setting the FMTA1-0 and FMTB1-0 bits independently (
Table
84
and
Table 85
). In 16bit Linear mode, the serial data is MSB first, 2’s complement format. In 8bit A-Law and
μ
-Law
Mode, the serial data is MSB first. PCM I/F formats can be used in both master and slave modes. SYNCA/B and
BICKA/B are output from the AK4671 in master mode, but must be input to the AK4671 in slave mode.
Mode
FMTA1
FMTA0
Format
0
0
0
Short Frame Sync
1
0
1
Long Frame Sync
2
1
0
MSB justified
3
1
1
I
2
S
Table 84. PCM I/F A Format
Mode
FMTB1
FMTB0
Format
0
0
0
Short Frame Sync
1
0
1
Long Frame Sync
2
1
0
MSB justified
3
1
1
I
2
S
Table 85. PCM I/F B Format
In modes 2 and 3, the SDTOA/B is clocked out on the falling edge (“
”) of BICKA/B and the SDTIA/B is latched on the
rising edge (“
”).
In Modes 0 and 1, PCM I/F A timing is changed by BCKPA and MSBSA bits,and PCM I/F B timing is changed by
BCKPB and MSBSB bits.
When BCKPA bit = “0”, the SDTOA is clocked out on the rising edge (“
”) of BICKA and the SDTIA is latched on the
falling edge (“
”). When BCKPA bit = “1”, the SDTOA is clocked out on the falling edge (“
”) of BICKA and the
SDTIA is latched on the rising edge (“
”).
MSBSA bit can shift the MSB position of SDTOA and SDTIA by half period of BICKA.
When BCKPB bit = “0”, the SDTOB is clocked out on the rising edge (“
”) of BICKB and the SDTIB is latched on the
falling edge (“
”). When BCKPB bit = “1”, the SDTOB is clocked out on the falling edge (“
”) of BICKB and the
SDTIB is latched on the rising edge (“
”).
MSBSB bit can shift the MSB position of SDTOB and SDTIB by half period of BICKB.
Format
16bit Linear
N/A
8bit A-Law
8bit
μ
-Law
(default)
Format
16bit Linear
N/A
8bit A-Law
8bit
μ
-Law
(default)
BICKA
16fs2
16fs2
32fs2
32fs2
Figure
See
Table 86
See
Table 88
Figure 92
Figure 93
(default)
BICKB
16fs2
16fs2
32fs2
32fs2
Figure
See
Table 87
See
Table 89
Figure 92
Figure 93
(default)
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