參數(shù)資料
型號(hào): AK4671EG
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類(lèi): Codec
英文描述: Stereo CODEC with MIC/RCV/HP-AMP
中文描述: 立體聲編解碼器麥克風(fēng)/垃圾車(chē)/惠普腺苷
文件頁(yè)數(shù): 152/164頁(yè)
文件大?。?/td> 1792K
代理商: AK4671EG
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)當(dāng)前第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)
[AK4671]
MS0666-E-00
2007/10
- 152 -
MIC Input Recording (Stereo)
FS3-0 bits
(Addr:01H, D7-4)
MIC Control
(Addr:05H, D7-0)
PMMICL/R bits
PMADL/R bits
(Addr:00H, D5-2)
ADC Internal
State
1111
0000
55H
AAH
Power Down
Initialize Normal State
Power Down
1059 / fs
(1)
(2)
(7)
ALC State
ALC Enable
ALC Disable
ALC Disable
(5)
ALC Control 1
(Addr:16H)
00H
05H
(3)
ALC Control 2
(Addr:14H)
E1H
E1H
(4)
ALC Control 3
(Addr:17H)
15H
01H
(8)
(6)
ALC Control 4
(Addr:18H)
02H
03H
02H
(9)
PMMP bit
(Addr:00H, D1)
Example:
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Pre MIC AMP: +15dB
MIC Power: On
ALC setting: Refer to Table 62
ALC: Enable
(2) Addr:05H, Data: AAH
(3) Addr:16H, Data:05H
(1) Addr:01H, Data:F4H
(4) Addr:14H, Data:E1H
(5) Addr:17H, Data:01H
(7) Addr:00H, Data:3FH
Recording
(8) Addr:00H, Data:01H
(6) Addr:18H, Data:03H
(9) Addr:18H, Data:02H
Figure 114. Stereo MIC Input Sequence
(MIC Recording: LIN1/RIN1
MICL/R
ADCL/R
ALC
Audio I/F
SDTO)
<Example>
This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to “
Figure
62
”.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1)
Set up a sampling frequency (FS3-0 bits). When the AK4671 is PLL mode, MIC and ADC should be powered-up in
consideration of PLL lock time after a sampling frequency is changed.
(2)
Set up Gain for MIC-Amp (Addr: 05H)
(3)
Set up Timer Select for ALC (Addr: 16H)
(4)
Set up REF value for ALC (Addr: 14H)
(5)
Set up LMTH1-0, RGAIN1-0 and LMAT1-0 bits (Addr: 17H)
(6)
Set up ALC bit (Addr: 18H)
(7)
Power Up MIC and ADC: PMMP = PMMICL = PMMICR = PMADL = PMADR bits = “0”
“1”
The initialization cycle time of ADC is 1059/fs=24ms@fs=44.1kHz.
After the ALC bit is set to “1” and ADC block is powered-up, the ALC operation starts from IVOL default value (0dB).
The time of offset voltage going to “0” after the ADC initialization cycle depends on both the time of analog input pin
going to the common voltage and the time constant of the offset cancel digital HPF. This time can be shorter by using
the following sequence:
At first, PMVCM and PMMP bits should set to “1”. Then, the ADC should be powered-up. The wait time to power-up
the ADC should be longer than 4 times of the time constant that is determined by the AC coupling capacitor at analog
input pin and the internal input resistance.
(8)
Power Down MIC and ADC: PMMP = PMMICL = PMMICR = PMADL = PMADR bits = “1”
“0”
When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is disabled
because the ADC block is powered-down. If the registers for the ALC operation are also changed when the sampling
frequency is changed, it should be done after the AK4671 goes to the manual mode (ALC bit = “0”) or ADC block is
powered-down (PMADL = PMADR bits = “0”). IVOL gain is not reset when PMADL = PMADR bits = “0”, and then
IVOL operation starts from the setting value when PMADL or PMADR bit is changed to “1”.
(9)
ALC Disable: ALC bit = “1”
“0”
相關(guān)PDF資料
PDF描述
AK4673 Stereo CODEC with MIC/HP-AMP and Touch Screen Controller
AK4673EG Stereo CODEC with MIC/HP-AMP and Touch Screen Controller
AK4682 Multi-channel CODEC with 2Vrms Stereo Selector
AK4682EQ Multi-channel CODEC with 2Vrms Stereo Selector
AK4683_07 Asynchronous Multi-Channel Audio CODEC with DIR/T
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4673 制造商:AKM 制造商全稱(chēng):AKM 功能描述:Stereo CODEC with MIC/HP-AMP and Touch Screen Controller
AK4673EG 制造商:AKM 制造商全稱(chēng):AKM 功能描述:Stereo CODEC with MIC/HP-AMP and Touch Screen Controller
AK4675 制造商:AKM 制造商全稱(chēng):AKM 功能描述:Stereo CODEC with MIC/RCV/HP/SPK-AMP
AK4675EG 制造商:AKM 制造商全稱(chēng):AKM 功能描述:Stereo CODEC with MIC/RCV/HP/SPK-AMP
AK4682 制造商:AKM 制造商全稱(chēng):AKM 功能描述:Multi-channel CODEC with 2Vrms Stereo Selector