參數(shù)資料
型號(hào): AK4671EG
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: Stereo CODEC with MIC/RCV/HP-AMP
中文描述: 立體聲編解碼器麥克風(fēng)/垃圾車/惠普腺苷
文件頁數(shù): 160/164頁
文件大?。?/td> 1792K
代理商: AK4671EG
[AK4671]
MS0666-E-00
2007/10
- 160 -
Receiver-Amp Output
OVR7-0 bits
(Addr:1BH, D7-0)
PMDAR bit
(Addr:00H, D7)
PML/RO1 bits
(Addr:0FH, D1-0)
18H
28H
RCP pin
RCN pin
(3)
(4)
(1)
DACR bit
(Addr:0AH, D0)
(10)
Normal Output
(6)
LOPS1 bit
(Addr:0FH, D2)
(5)
(7)
(8)
(11)
L1VL2-0 bits
(Addr:08H, D2-0)
101
100
PMSRB bit
(Addr:53H, D1)
EQ bit
(Addr:18H, D3)
0
1
0
(2)
(9)
SRMXR1-0 bits
(Addr:15H, D7-6)
00
01
RCV bit
(Addr:0FH, D5)
>1 ms
Example:
PCM I/F A: Slave Mode
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
Sampling Frequency: 8kHz
Digital Volume Level:
8dB
5 band EQ: Enable
(1) Addr:08H, Data:B4H
Addr:15H, Data:40H
Addr:0AH, Data:01H
Addr:0FH, Data:20H
(3) Addr:1BH, Data:28H
(4) Addr:0FH, Data:24H
(5) Addr:53H, Data:06H
Addr:00H, Data:81H
Addr:0FH, Data:27H
(6) Addr:0FH, Data:23H
Phone Call
(7) Addr:0FH, Data:27H
(8) Addr:53H, Data:04H
Addr:00H, Data:01H
Addr:0FH, Data:24H
(10) Addr:0AH, Data:00H
(11) Addr:0FH, Data:20H
(2) Addr:18H, Data:0AH
(9) Addr:18H, Data:02H
Figure 125. Receiver-Amp Output Sequence
(Phone Call Rx: SDTIA
PCM I/F A
SRC-B
EQ
DATT
DACR
RCP/RCN)
<Example>
At first, clocks should be supplied according to “
Clock Set Up
” sequence. Also, SRC-B, DAC and Receiver-Amp
should be powered-up in consideration of PLLBT lock time.
(1)
Set up the path of “SDTIA
DAC
Receiver-Amp”: SRMXR1-0 bits = “00”
“01”, DACR bit = “0”
“1”, RCV bit = “0”
“1”
Set up analog volume for Receiver-Amp (Addr: 08H, L1VL2-0 bits)
(2)
Enable 5-band Equalizer: EQ bit = “0”
“1” (Boost amount is selected by Addr = 50H-52H.)
(3)
Set up the output digital volume (Addr: 1BH)
When OVOLC bit is “1” (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(4)
Enter power-save mode of Receiver-Amp: LOPS1 bit = “0”
“1”
(5)
Power-up SRC-B, DAC and Receiver-Amp: PMSRB bit = PMDAR = PMLO1 = PMRO1 bits = “0”
“1”
RCN pin rise up to VCOM voltage after PMLO1 and PMRO1 bits are changed to “1”.
(6)
Exit power-save mode of Receiver-Amp: LOPS1 bit = “1”
“0”
LOPS1 bit should be set to “0” after PCN pin rise up. Receiver-Amp goes to normal operation by setting
LOPS1 bit to “0”.
(7)
Enter power-save mode of Receiver-Amp: LOPS1 bit: “0”
“1”
(8)
Power-down SRC-B, DAC and Receiver-Amp: PMSRB bit = PMDAR = PMLO1 = PMRO1 bits = “1”
“0”
Receiver-Amp becomes to power-down mode.
(9)
Disable 5-band Equalizer: EQ bit = “1”
“0”
(10)
Disable the path of “DAC
Receiver-Amp”: DACR bit = “1”
“0”
(11)
Exit power-save mode of Receiver-Amp: LOPS1 bit = “1”
“0”
LOPS1 bit should be set to “0” after Receiver-Amp power-down.
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