
[AK4648]
MS0625-E-01
2007/06
- 65 -
LOUT pin
ROUT pin
1
μ
F
220
Ω
20k
Ω
Figure 45. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit)
<Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)>
(2)
P M LO bit
LO P S bit
LO U T , R O U T pins
(1)
N orm al O utput
(3)
(4)
(5)
(6)
≥
300 m s
≥
300 m s
Figure 46. Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)
(1)
Set LOPS bit = “1”. Stereo line output enters the power-save mode.
(2)
Set PMLO bit = “1”. Stereo line output exits the power-down mode.
LOUT and ROUT pins rise up to VCOM voltage. Rise time is 200ms (max. 300ms) at C=1
μ
F and
AVDD=3.3V.
(3)
Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode.
Stereo line output is enabled.
(4)
Set LOPS bit = “1”. Stereo line output enters power-save mode.
(5)
Set PMLO bit = “0”. Stereo line output enters power-down mode.
LOUT and ROUT pins fall down to VSS1. Fall time is 200ms (max. 300ms) at C=1
μ
F and AVDD=3.3V.
(6)
Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode.