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參數(shù)資料
| 型號： | AK4648EC |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | Stereo CODEC with MIC/HP/SPK-AMP |
| 中文描述： | 立體聲編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 33/119頁 |
| 文件大?。?/td> | 1272K |
| 代理商： | AK4648EC |
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[AK4648]
MS0625-E-01
2007/06
- 33 -
When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3 and FS1-0 bits. (Table
7).
FS2 bit is “don’t care”.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
0
0
x
0
1
0
x
0
2
0
x
1
3
0
x
1
6
1
x
1
7
1
x
1
Others
Others
Sampling Frequency Range
7.35kHz
≤
fs
≤
8kHz
8kHz < fs
≤
12kHz
12kHz < fs
≤
16kHz
16kHz < fs
≤
24kHz
24kHz < fs
≤
32kHz
32kHz < fs
≤
48kHz
N/A
0
1
0
1
0
1
(default)
(x: Don’t care)
Table 7. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)
■
PLL Unlock State
1) PLL Master Mode (AIN3 bit = “0”; PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BICK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is
“1” before the PLL goes to lock state after PMPLL bit = “0”
“1”. If MCKO bit is “0”, MCKO pin goes to “L” (Table
8).
After the PLL is locked, the first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
PLL State
MCKO bit = “0”
MCKO bit = “1”
After that PMPLL bit “0”
“1”
“L” Output
PLL Unlock (except case above)
“L” Output
PLL Lock
“L” Output
Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
2) PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0”
“1”.
Then, the clock selected by Table 10 is output from MCKO pin when PLL is locked. ADC and DAC output invalid data
when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL and DACH bits.
BICK pin
LRCK pin
Invalid
Invalid
Table 10
“L” Output
Invalid
Table 11
“L” Output
Invalid
1fs Output
MCKO pin
PLL State
MCKO bit = “0”
“L” Output
“L” Output
“L” Output
MCKO bit = “1”
Invalid
Invalid
Output
Just after PMPLL bit “0”
“1”
PLL Unlock (except case above)
PLL Lock
Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
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相關(guān)代理商/技術(shù)參數(shù) |
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| AK4649 | 制造商:AKM 制造商全稱:AKM 功能描述:24bit Stereo CODEC with MIC/SPK-AMP |
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| AK4649VN | 功能描述:IC CODEC AUDIO 32QFN 制造商:akm semiconductor inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):初步 類型:音頻 數(shù)據(jù)接口:I2C 分辨率（位）:24 b ADC/DAC 數(shù):1 / 1 三角積分:- 信噪比，ADC/DAC（db）（典型值）:- 動(dòng)態(tài)范圍，ADC/DAC（db）（典型值）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤 供應(yīng)商器件封裝:32-QFN（5x5） 標(biāo)準(zhǔn)包裝:1,000 |
| AK4650 | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC |
| AK4650VG | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC |
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