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參數(shù)資料
| 型號： | AK4343EN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Stereo DAC with HP/RCV/SPK-AMP |
| 中文描述： | 立體聲DAC惠普/垃圾車/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 69/98頁 |
| 文件大?。?/td> | 851K |
| 代理商： | AK4343EN |
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ASAHI KASEI
[AK4343]
MS0478-E-01
2006/10
- 69 -
Register Definitions
Addr
Register Name
00H
Power Management 1
Default
PMDAC: DAC Power Management
0: Power-down (Default)
1: Power-up
PMLO: Stereo Line Out Power Management
0: Power-down (Default)
1: Power-up
PMSPK: Speaker-Amp Power Management
0: Power-down (Default)
1: Power-up
PMMIN: MIN Input Power Management
0: Power-down (Default)
1: Power-up
PMMIN or PMAINL3 bit should be set to “1” for playback.
PMVCM: VCOM Power Management
0: Power-down (Default)
1: Power-up
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when all power management bits of 00H, 01H, 02H, 10H, 20H and MCKO bits are “0”.
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value.
When all power management bits are “0” in the 00H, 01H, 02H and 20H addresses and MCKO bit is “0”, all blocks are
powered-down. The register values remain unchanged.
When DAC is not used, external clocks may not be present. When DAC is used, external clocks must always be
present.
D7
0
0
D6
D5
D4
D3
D2
D1
0
0
D0
0
0
PMVCM
0
PMMIN
0
PMSPK
0
PMLO
0
PMDAC
0
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AK4343VNP-L | 制造商:AKM Semiconductor Inc 功能描述:AK4343VNP-L |
| AK4344 | 制造商:AKM 制造商全稱:AKM 功能描述:100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC |
| AK4344_10 | 制造商:AKM 制造商全稱:AKM 功能描述:100dB 96kHz 24-Bit Stereo 3.3V ΔΣ DAC |
| AK4344ET | 制造商:AKM 制造商全稱:AKM 功能描述:100dB 96kHz 24-Bit Stereo 3.3V ΔΣ DAC |
| AK4345 | 制造商:AKM 制造商全稱:AKM 功能描述:100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT |
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