
ASAHI KASEI 
[AK4343] 
MS0478-E-01 
2006/10 
- 32 - 
System Reset
Upon power-up, the AK4343 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset 
to their initial values. 
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1”. The initialization 
cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are 
internally forced to a 2’s compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is 
complete. 
 Audio Interface Format 
Four types of data formats are available and are selected by setting the DIF1-0 bits (seeTable 17). In all modes, the serial 
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK 
and BICK are output from the AK4343 in master mode, but must be input to the AK4343 in slave mode. 
Mode 
DIF1 bit 
DIF0 bit 
SDTI (DAC) 
0 
0 
0 
DSP Mode 
1 
0 
1 
LSB justified 
2 
1 
0 
MSB justified 
3 
1 
1 
I
2
S compatible 
Table 17. Audio Interface Format 
In modes 1, 2 and 3, the SDTI is latched on the rising edge (“
↑
”) of BICK. 
In Modes 0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 18). 
DIF1 
DIF0 
MSBS 
BCKP 
Audio Interface Format 
MSB of SDTI is latched by the falling edge (“
↓
”) of the BICK 
just after the rising edge (“
↑
”) of the first BICK after the rising 
edge (“
↑
”) of LRCK. 
MSB of SDTI is latched by the rising edge (“
↑
”) of the BICK 
just after the falling edge (“
↓
”) of the first BICK after the rising 
edge (“
↑
”) of LRCK. 
MSB of SDTI is latched by the 2nd falling edge (“
↓
”) of the 
BICK after the rising edge (“
↑
”) of LRCK. 
MSB of SDTI is latched by the 2nd rising edge (“
↑
”) of the 
BICK after the rising edge (“
↑
”) of LRCK.. 
Table 18. Audio Interface Format in Mode 0 
BICK 
≥
 32fs 
≥
 32fs 
≥
 32fs 
≥
 32fs 
Figure 
Table 18 
Figure 28 
Figure 29 
Figure 30 
Default 
Figure 
0 
0 
Figure 24
Default
0 
1 
Figure 25
1 
0 
Figure 26
0 
0 
1 
1 
Figure 27