參數(shù)資料
型號(hào)： AK4343EN
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： Stereo DAC with HP/RCV/SPK-AMP
中文描述： 立體聲DAC惠普/垃圾車/胰腎聯(lián)合移植腺苷
文件頁數(shù)： 31/98頁
文件大?。?/td> 851K
代理商： AK4343EN
ASAHI KASEI
[AK4343]
MS0478-E-01
2006/10
- 31 -
EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4343 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The
input frequency of MCKI is selected by FS1-0 bits (see Table 14).
Mode
FS3-2 bits
FS1 bit
FS0 bit
MCKI Input
Frequency
256fs
1024fs
256fs
512fs
Sampling Frequency
Range
7.35kHz
～
48kHz
7.35kHz
～
13kHz
7.35kHz
～
48kHz
7.35kHz
～
26kHz
0
1
2
3
Don’t care
Don’t care
Don’t care
Don’t care
Table 14. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
0
0
1
1
0
1
0
1
Default
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through LOUT/ROUT pins at fs=8kHz is shown in Table 15.
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
83dB
93dB
93dB
256fs
512fs
1024fs
Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI should always be present whenever the DAC is in operation (PMDAC bit = “1”). If MCKI is not provided, the
AK4343 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic
internally. If MCKI is not present, the DAC should be in the power-down mode (PMDAC bit = “0”).
AK4343
DSP or
μ
P
MCKI
BICK
LRCK
SDTI
BCLK
LRCK
SDTO
MCKO
1fs
32fs or 64fs
MCLK
256fs, 512fs or 1024fs
Figure 23. EXT Master Mode
BCKO bit
BICK Output
Frequency
32fs
64fs
0
1
Default
Table 16. BICK Output Frequency at Master Mode
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
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AK4343VNP-L 制造商:AKM Semiconductor Inc 功能描述:AK4343VNP-L
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