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參數(shù)資料
| 型號： | AK4343EN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Stereo DAC with HP/RCV/SPK-AMP |
| 中文描述： | 立體聲DAC惠普/垃圾車/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 25/98頁 |
| 文件大?。?/td> | 851K |
| 代理商： | AK4343EN |
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ASAHI KASEI
[AK4343]
MS0478-E-01
2006/10
- 25 -
PLL Mode (AIN3 bit = “0”, PMPLL bit = “1”)
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 5, whenever the AK4343 is supplied to a stable clocks after
PLL is powered-up (PMPLL bit = “0”
→
“1”) or sampling frequency changes. When AIN3 bit = “1”, the PLL is not
available.
1) Setting of PLL Mode
R and C of
VCOC pin
R[
]
6.8k
-
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
Input
Frequency
C[F]
220n
-
4.7n
10n
4.7n
10n
4.7n
4.7n
4.7n
4.7n
10n
10n
PLL Lock
Time
(max)
160ms
-
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
0
1
2
3
4
5
6
7
12
13
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
LRCK pin
N/A
BICK pin
BICK pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
N/A
1fs
-
32fs
64fs
Default
11.2896MHz
12.288MHz
12MHz
24MHz
13.5MHz
27MHz
Others
Others
Table 5. Setting of PLL Mode (*fs: Sampling Frequency)
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 6.
Mode
FS3 bit
FS2 bit
FS1 bit
0
0
0
0
1
0
0
0
2
0
0
1
3
0
0
1
4
0
1
0
5
0
1
0
6
0
1
1
7
0
1
1
10
1
0
1
11
1
0
1
14
1
1
1
15
1
1
1
Others
Others
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin)
When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3 and FS1-0 bits. (See
Table 7).
FS2 bit is “don’t care”.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
0
0
Don’t care
0
1
0
Don’t care
0
2
0
Don’t care
1
3
0
Don’t care
1
6
1
Don’t care
1
7
1
Don’t care
1
Others
Others
Table 7. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)
FS0 bit
0
1
0
1
0
1
0
1
0
1
0
1
Sampling Frequency
8kHz
12kHz
16kHz
24kHz
7.35kHz
11.025kHz
14.7kHz
22.05kHz
32kHz
48kHz
29.4kHz
44.1kHz
N/A
Default
Sampling Frequency Range
7.35kHz
≤
fs
≤
8kHz
8kHz < fs
≤
12kHz
12kHz < fs
≤
16kHz
16kHz < fs
≤
24kHz
24kHz < fs
≤
32kHz
32kHz < fs
≤
48kHz
N/A
0
1
0
1
0
1
Default
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4345 | 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT |
| AK4345ET | 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT |
| AK4346 | 3.3V 192kHz 24-Bit 6-Channel DAC |
| AK4346EF | 3.3V 192kHz 24-Bit 6-Channel DAC |
| AK4346VF | 3.3V 192kHz 24-Bit 6-Channel DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4343VNP-L | 制造商:AKM Semiconductor Inc 功能描述:AK4343VNP-L |
| AK4344 | 制造商:AKM 制造商全稱:AKM 功能描述:100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC |
| AK4344_10 | 制造商:AKM 制造商全稱:AKM 功能描述:100dB 96kHz 24-Bit Stereo 3.3V ΔΣ DAC |
| AK4344ET | 制造商:AKM 制造商全稱:AKM 功能描述:100dB 96kHz 24-Bit Stereo 3.3V ΔΣ DAC |
| AK4345 | 制造商:AKM 制造商全稱:AKM 功能描述:100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT |
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