tPER Write Address: 364 D" />
參數(shù)資料
型號(hào): AFE7222IRGC25
廠商: Texas Instruments
文件頁數(shù): 97/106頁
文件大小: 0K
描述: IC AFE 12BIT 65/130MSPS 64VQFN
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
通道數(shù): 4
功率(瓦特): 610mW
電壓 - 電源,模擬: 2.85 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.7 V ~ 1.9 V
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 296-30067-6
SET CONVERSION START=1
SDATA
SCLK
SEN
DO11DO10 DO9
DATA LATENCY = 27.5 CLOCKS
tPER
Write Address: 364 Data: 01
SHIGH (INTERNAL SAMPLING
CLOCK)
DO8 DO7 DO6 DO5 DO4 DO3
DO2 DO1 DO0
AUXADC input sampled here
AUXADC goes back to sampling mode
SDOUT
20 clocks
DATA PROPAGATION DELAY = 20 ns
AUXDAC_A
(Pin)
AUXDAC_A_N
(Internal node)
REXT
RINT
I
AUX_DAC
AVDD3_AUX (3 V)
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
10.8.1 Enabling the Auxiliary ADC
The Auxiliary ADCs are disabled by default.
Below is the timing diagram illustrating the Aux ADC operation.
Before starting conversion, set bit EN_AUX_ADC to '1'. Also set WHAT_IS_SDOUT<1:0> to configure
SDOUT as a digital output pin.
Figure 10-16. AUX ADC Timing Diagram
Note that throughout the Aux ADC conversion, SEN is kept low (active). Also keep SDATA low once the
CONV_START bit has been written.
To get out of Aux ADC conversion mode, pull SEN high, then pull it low again and write the bit to make
CONV_START=0.
10.9 Auxiliary DAC
The schematic of the Auxiliary DAC (for channel A) is shown below.
Figure 10-17. Auxiliary DAC Schematic
The Auxiliary DAC is a 12-bit current output DAC with the current steered into the AUXDAC_A pin
dependent on the digital code. The data format of the Auxiliary DAC input is offset binary.
REXT is the external connected to the AUXDAC_A pin and along with the value of the full scale current,
sets the full scale output voltage range. For zero input code, voltage on AUXDAC_A is equal to 0 V.
For maximum input code, voltage on AUXDAC_A is equal to IAUX_DAC*REXT.
IAUX_DAC is the full scale current of the Auxiliary DAC, and can be programmed from 2.5 mA to 7.5 mA
(using bits FS_AUXDACI<3:0>).
For best linearity, limit the maximum voltage at AUXDAC_A to 1.5V. For example, with IAUX_DAC set to 5
mA, and REXT set to 300 Ohm, the voltage on AUXDAC_A will swing from 0 to 1.5V.
90
DIGITAL INTERFACE
Copyright 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE7222 AFE7225
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