參數(shù)資料
型號(hào)： AFE7222IRGC25
廠商： Texas Instruments
文件頁數(shù)： 27/106頁
文件大?。?/td> 0K
描述： IC AFE 12BIT 65/130MSPS 64VQFN
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
通道數(shù)： 4
功率（瓦特）： 610mW
電壓 - 電源，模擬： 2.85 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.7 V ~ 1.9 V
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤（9x9）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 296-30067-6
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
Register Name – CONFIG11 – Address 0x110 Default = 0x00 (Optionally Synced )
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_QMC_OFFSETA(4:0)
TX_QMC_GAINA(2:0)
TX_QMC_OFFSETA(4:0) – Lower 5 bits of DAC A Offset Correction .
TX_QMC_GAINA(2:0) – Lower 3 bits of the 11 bit QMC Gain word for DAC A. The upper 8 bits are in
CONFIG12 register.The full 11 bit TX_QMC_GAINA(10:0) word is formatted as UNSIGNED with a range
or 0 to 1.9990 . The implied decimal point for the multiplication is between bits (9) and (10).
Register Name – CONFIG12 – Address 0x111 Default = 0x00 (Synced )
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_QMC_GAINA(10:3)
TX_QMC_GAINA(10:3) –Upper 8 bits if the 11 bit QMC Gain word for DAC A.
Register Name – CONFIG13 – Address 0x112 Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_QMC_OFFSETB(12:5)
TX_QMC_OFFSETB(12:5) –Upper 8 bits of DAC B Offset Correction. The lower 5 bits are in CONFIG14
Register.
Register Name – CONFIG14 – Address 0x113 Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_QMC_OFFSETB(4:0)
TX_QMC_GAINB(2:0)
TX_QMC_OFFSETB(4:0) – Lower 5 bits of DAC B Offset Correction .
TX_QMC_GAINB(2:0) – Lower 3 bits of the 11 bit QMC Gain word for DAC B. The upper 8 bits are in
CONFIG15 register.The full 11 bit TX_QMC_GAINB(10:0) word is formatted as UNSIGNED with a range
or 0 to 1.9990.
Register Name – CONFIG15 – Address 0x114 Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_QMC_GAINB(10:3)
TX_QMC_GAINB(10:3) – Upper 8 bits if the 11 bit QMC Gain word for DAC B.
Register Name – CONFIG16 – Address 0x115 Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_QMC_PHASE(9:2)
TX_QMC_PHASE(9:2) – Upper Upper 8 bits if the 10 bit QMC Phase word. The lower two bits are in the
CONFIG17 register. The full QMC_PHASE(9:0) correction word is formatted as 2s complement and
scaled to occupy a range of -0.125 to 0.12475. To acomplish QMC Phase correction, this value is
multiplied by the current Q sample, then summed to the I sample.
Register Name – CONFIG17 – Address 0x116 Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_QMC_PHASE(1:0)
TX_QMC_PHASE(1:0) – Lower 2 bits of the 10 bit QMC Phase word .
Copyright 2011–2012, Texas Instruments Incorporated
REGISTER DESCRIPTIONS
27
Product Folder Link(s): AFE7222 AFE7225
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