參數(shù)資料
型號： AFE7222IRGC25
廠商： Texas Instruments
文件頁數(shù)： 95/106頁
文件大?。?/td> 0K
描述： IC AFE 12BIT 65/130MSPS 64VQFN
標準包裝： 1
位數(shù)： 12
通道數(shù)： 4
功率（瓦特）： 610mW
電壓 - 電源，模擬： 2.85 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.7 V ~ 1.9 V
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤（9x9）
包裝： 標準包裝
其它名稱： 296-30067-6
CLKINP
5 kW
VCM
5 kW
2 pF
20 W
Lpkg
~ 1 nH
Cbond
~ 1 pF
Lpkg
~ 1 nH
Cbond
~ 1 pF
Resr
~100 W
Resr
~
CLKINN
Differential Clock buffer
Ceq
Ceq ~ 1 to 3 pF, equivalent input capacitance of differential
clock buffer
100 W
12-Bit
SAR ADC
AUXADC_A
AUXADC_B
Serializer
SDOUT
SCLK
MODE_INPUT<1:0>
SHIGH
BYPASSZ_BUF
Input
Buffer
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
Figure 10-14. Input Clock Equivalent Circuit
10.8 Auxiliary ADC
The schematic of the Auxiliary ADC is shown below.
Figure 10-15. Auxiliary ADC Schematic
The Auxiliary ADC comprises a 12-bit SAR ADC with a high impedance input buffer that is bypassed by
default (BYPASSZ_BUF=0). The Auxiliary ADC can select its input from 2 external pins called
AUXADC_A and AUXADC_B. This selection is done using the bits MODE_INPUT <1:0>. The conversion
is started by setting bit CONV_START to 1, and SCLK is used as the conversion clock. The SAR ADC
converts the selected input and the 12-bit output is serialized using the SCLK and given out on the
SDOUT pin. After setting CONV_START to 1, the Auxiliary ADC can be configured for either a single
conversion, multiple conversions or in continuous conversion mode.
With the input buffer bypassed, the input range of the Auxiliary ADC is 0-1.5V when RANGE_AUXADC is
set to 0. When the Auxiliary ADC is converting, the SAR ADC draws switching current from the input pin if
the input buffer is bypassed. This may not be desirable for applications where the voltage being monitored
does not have drive capability. With the input buffer introduced in the path of the input, the AUXADC
inputs are high impedance and do not draw current. However, the input voltage range (at the AUXADC
pins) is slightly reduced to 0.1-1.5V.
With RANGE_AUXADC set to 1, the input range is increased to 0-DVDD18 with the buffer bypassed and
0.1-(DVDD18-0.1)V with the buffer enabled.
Copyright 2011–2012, Texas Instruments Incorporated
DIGITAL INTERFACE
89
Product Folder Link(s): AFE7222 AFE7225
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