參數(shù)資料
型號(hào): AFE7222IRGC25
廠商: Texas Instruments
文件頁數(shù): 49/106頁
文件大?。?/td> 0K
描述: IC AFE 12BIT 65/130MSPS 64VQFN
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
通道數(shù): 4
功率(瓦特): 610mW
電壓 - 電源,模擬: 2.85 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.7 V ~ 1.9 V
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 296-30067-6
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
5.5
CLOCKING CONTROL REGISTERS
Register Name – CONFIG115 – Address 0x23C, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
STR_CTRL<1:0>
DIV_ADC<1:0>
DIV_DAC<1:0>
STR_CTRL<1:0>: Controls the strength of the RX CMOS output clock (ADC_DCLKOUT) and data buffers
(increases the strength). When running at Fs higher than 90 MSPS, set to ‘10’ to get more timing margins.
Enabling this mode might increase the digital noise coupled to analog and may degrade the ADC SNR by
up to a dB.
DIV_ADC<1:0>: Divides the clock going to the ADC.
DIV_ADC<1:0>
DIVISION FACTOR
00
Default (no division)
01
2
10
4
11
2
DIV_DAC<1:0>: Divides the clock going to the DAC.
DIV_ADC<1:0>
DIVISION FACTOR
00
Default (no division)
01
2
10
4
11
2
Register Name – CONFIG116 – Address 0x23D, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
PLL_ENABLE
PLL_DIVM<1:0>
PLL_DIVN
PLL_ENABLE: Setting this bit enables the PLL. Output clock of the PLL is either 2X or 4X of Fs (input
clock rate).
PLL_DIVN: Selects multiplication by 4 (default is multiplication by 2).
PLL_DIVM<1:0>: Different values as listed in the below table need to be programmed for different Fs
ranges.
PLL_DIVM<1:0>
FS in MSPS
Multiplication by 2
Multiplication by 4
15-20
3
2
20-35
2
1
35-80
1
0
> 80-180
0
Out of range
While operating PLL with a multiplication factor set by PLL_DIVN = X, there can be significant spurs at
(NFs/X+/-Fin) where N is an integer. At Fin = 10 MHz, these spurs can be about -60dBc.
Copyright 2011–2012, Texas Instruments Incorporated
REGISTER DESCRIPTIONS
47
Product Folder Link(s): AFE7222 AFE7225
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