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參數(shù)資料
型號(hào)： AFE7222IRGC25
廠商： Texas Instruments
文件頁(yè)數(shù)： 75/106頁(yè)
文件大?。?/td> 0K
描述： IC AFE 12BIT 65/130MSPS 64VQFN
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
通道數(shù)： 4
功率（瓦特）： 610mW
電壓 - 電源，模擬： 2.85 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.7 V ~ 1.9 V
封裝/外殼： 64-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤(pán)（9x9）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： 296-30067-6
INP_A_ADC
12b
RX ADC B
12b
RX ADC A
INN_A_ADC
INP_B_ADC
INN_B_ADC
C
o
a
rs
e
M
ix
e
r
(C
M
IX
)
RX RMS /
Peak
Power Meter
Q
M
C
G
a
in
/
P
h
a
s
e
SYNC
/2
H
B
F
D
e
c
im
a
ti
o
n
Q
M
C
O
ff
s
e
t
SYNC
RX Output A
F
in
e
M
ix
e
r
(F
M
IX
)
NCO
SYNC
RX Output B
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
9
APPLICATION INFORMATION
9.1
DEVICE DESCRIPTION
The AFE7225/7222 is designed to offer small footprint, high performance, low power and flexibility in
applications that require half or full duplex software defined radios. The receive path consists of dual 12-bit
125MSPS ADCs, a digital quadrature modulation correction block, FCLK/4 digital frequency shifter and /2
decimation filter. The transmit path consists of dual 12-bit 250MSPS DACs, a digital quadrature
modulation correction block, FCLK /4 digital frequency shifter, and x2/x4 interpolation filters as well as a
FIFO. A peak/rms power meter is available to the receive path. Fine Mixers with NCOs are available for
both receive and transmit path. These NCOs can be programmed independently. The primary digital
interface is selectable as either interleaved parallel CMOS or serialized LVDS. Device control is provided
via SPI (serial peripheral interface).
An auxiliary 12-bit 100kSPS ADC with two single-ended voltage inputs via a multiplexer is provided for
voltage monitoring. A dual auxiliary 12-bit 2MSPS single-ended current source output DAC is available for
control and/or board calibration. Most blocks can be independently powered on/off as needed to save
power. All of this capability is available in a small 9mm x 9mm 64-pin QFN package.
9.2
RECEIVER SIGNAL CHAIN
Figure 9-1. Signal Chain
9.3
RECEIVE ADC
The dual receive ADCs are created using a pipeline architecture and are powered from a 1.8V analog
supply (AVDD18_ADC). The common-mode of the differential inputs is 0.95V. A VCM pin is provided
which outputs the common-mode voltage for use in setting up the proper input level. If the VCM pin
cannot be used in your application, ensure that the analog inputs are centered at 0.95V. The full scale
range of the inputs is 2.0Vpp differential, or 0.95 ± 0.5V on both INN and INP pins.
The receive ADCs are capable of under-sampling intermediate frequencies (IF) at high frequency. The
3dB full power input bandwidth (FPBW) is approximately 550MHz. Good distortion and noise is maintained
to ~230MHz. The dual ADCs can be used to capture complex I/Q inputs from a quadrature demodulator,
or two independent IFs or used in a diversity configuration. In order to obey the Nyquist-Shannon
sampling theorem, ensure that the bandwidth to be sampled does not exceed FADCCLK/2. An external
anti-aliasing filter is recommended that confines the analog input energy to a single Nyquist band (multiple
of FADCCLK/2) to avoid unwanted aliasing and reduced overall performance.
9.4
RECEIVE DECIMATION FILTER
The user has the option of a decimation filter in the receive data path. The decimation filter can be used to
reduce the ADC data sample rate by half. The extra sampling bandwidth could be used for processing
gain and to ease the roll-off requirements of an external anti-aliasing filter. The decimation filter is a 43 tap
half-band filter. The transition band is from 0.38 to 0.62 of FADCCLK/4, and the stop band attenuation is
greater than 80dB. The pass-band ripple is less than 0.1dB. Coefficients 1 to 22 are listed. Coefficients 23
to 43 are the same as those from 22 to 1.
70
APPLICATION INFORMATION
Copyright 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE7222 AFE7225
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