參數(shù)資料
型號： ADV7393EBZ
廠商： Analog Devices, Inc.
英文描述： Low Power, Chip Scale 10-Bit SD/HD Video Encoder
中文描述： 低功耗，芯片尺寸10位標清/高清視頻編碼器
文件頁數(shù)： 93/96頁
文件大?。?/td> 1209K
代理商： ADV7393EBZ
ADV7390/ADV7391/ADV7392/ADV7393
Table 107. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x30
0x2C
720p @ 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Rev. 0 | Page 93 of 96
Table 108. 16-Bit 720p YCrCb In, YPrPb Out
Subaddress
Setting Description
0x17
0x02
0x00
0x1C
0x01
0x10
0x30
0x28
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
720p @ 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
0x31
0x01
Table 109. 16-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x2C
720p @ 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 110. 16-Bit 720p YCrCb In, RGB Out
Subaddress
Setting Description
0x17
0x02
0x00
0x1C
0x01
0x10
0x02
0x10
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
720p @ 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
0x30
0x28
0x31
0x01
Table 111. 16-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x30
0x6C
1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 112. 16-Bit 1080i YCrCb In, YPrPb Out
Subaddress
Setting
0x17
0x02
0x00
0x1C
0x01
0x10
0x30
0x18
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
1080i @ 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
0x31
0x01
Table 113. 16-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x6C
1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 114. 16-Bit 1080i YCrCb In, RGB Out
Subaddress
Setting
0x17
0x02
0x00
0x1C
0x01
0x10
0x02
0x10
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
1080i @ 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
0x30
0x18
0x31
0x01
Table 115. 8-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x2C
720p @ 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 116. 10-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x2C
720p @ 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x33
0x6C
10-bit input enabled.
相關(guān)PDF資料
PDF描述
ADV7400AKSTZ-80 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
ADV7400AKSTZ-801 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
ADV7400ABSTZ-1101 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
ADV7400AKSTZ-110 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
ADV7400AKSTZ-1101 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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ADV73946604 制造商:LG Corporation 功能描述:Frame Assembly
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