參數(shù)資料
型號： ADV7393EBZ
廠商： Analog Devices, Inc.
英文描述： Low Power, Chip Scale 10-Bit SD/HD Video Encoder
中文描述： 低功耗，芯片尺寸10位標(biāo)清/高清視頻編碼器
文件頁數(shù)： 90/96頁
文件大小： 1209K
代理商： ADV7393EBZ
ADV7390/ADV7391/ADV7392/ADV7393
ENHANCED DEFINITION
Rev. 0 | Page 90 of 96
Table 89. ED Configuration Scripts
Input Format
Input Data Width
525p
8-Bit DDR
525p
8-Bit DDR
525p
10-Bit DDR
525p
10-Bit DDR
525p
16-Bit SDR
525p
16-Bit SDR
525p
16-Bit SDR
525p
16-Bit SDR
625p
8-Bit DDR
625p
8-Bit DDR
625p
10-Bit DDR
625p
10-Bit DDR
625p
16-Bit SDR
625p
16-Bit SDR
625p
16-Bit SDR
625p
16-Bit SDR
Synchronization Format
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
Output Color Space
YPrPb
RGB
YPrPb
RGB
YPrPb
YPrPb
RGB
RGB
YPrPb
RGB
YPrPb
RGB
YPrPb
YPrPb
RGB
RGB
Table Number
Table 98
Table 100
Table 99
Table 101
Table 90
Table 91
Table 92
Table 93
Table 102
Table 104
Table 103
Table 105
Table 94
Table 95
Table 96
Table 97
Table 90. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x10
ED-SDR input mode.
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 91. 16-Bit 525p YCrCb In, YPrPb Out
Subaddress
Setting Description
0x17
0x02
0x00
0x1C
0x01
0x10
0x30
0x00
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p @ 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
0x31
0x01
Table 92. 16-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x10
ED-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 93. 16-Bit 525p YCrCb In, RGB Out
Subaddress
Setting
0x17
0x02
0x00
0x1C
0x01
0x10
0x02
0x10
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p @ 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
0x30
0x00
0x31
0x01
Table 94. 16-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x10
ED-SDR input mode.
0x30
0x1C
625p @ 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 95. 16-Bit 625p YCrCb In, YPrPb Out
Subaddress
Setting
0x17
0x02
0x00
0x1C
0x01
0x10
0x30
0x18
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p @ 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
0x31
0x01
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