參數(shù)資料
型號: ADV7393EBZ
廠商: Analog Devices, Inc.
英文描述: Low Power, Chip Scale 10-Bit SD/HD Video Encoder
中文描述: 低功耗,芯片尺寸10位標(biāo)清/高清視頻編碼器
文件頁數(shù): 86/96頁
文件大?。?/td> 1209K
代理商: ADV7393EBZ
ADV7390/ADV7391/ADV7392/ADV7393
Table 67. 10-Bit 525i YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x80
0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x88
0x10
10-bit input enabled.
Rev. 0 | Page 86 of 96
Table 68. 10-Bit 525i YCrCb In, RGB Out
Subaddress
Setting Description
0x17
0x02
0x00
0x1C
0x01
0x00
0x02
0x10
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
10-bit input enabled.
Timing Mode 2 (Slave). HSYNC/VSYNC
synchronization.
0x80
0x10
0x82
0xC9
0x88
0x8A
0x10
0x0C
Table 69. 16-Bit 525i YCrCb In, YPrPb Out
Subaddress
Setting Description
0x17
0x02
0x00
0x1C
0x01
0x00
0x80
0x10
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. pedestal enabled.
16-bit input enabled.
Timing Mode 2 (Slave). HSYNC/VSYNC
synchronization.
0x82
0xC9
0x88
0x8A
0x08
0x0C
Table 70. 16-Bit 525i YCrCb In, RGB Out
Subaddress
Setting
0x17
0x02
0x00
0x1C
0x01
0x00
0x02
0x10
Description
Software reset
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
16-bit input enabled.
Timing Mode 2 (Slave). HSYNC/VSYNC
synchronization.
0x80
0x10
0x82
0xC9
0x88
0x8A
0x08
0x0C
Table 71. 16-Bit 525i RGB In, YPrPb Out
Subaddress
Setting
0x17
0x02
0x00
0x1C
0x01
0x00
0x80
0x10
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
RGB input enabled.
16-bit input enabled.
Timing Mode 2 (Slave). HSYNC/VSYNC
synchronization.
0x82
0xC9
0x87
0x88
0x8A
0x80
0x08
0x0C
Table 72. 16-Bit 525i RGB In, CVBS/Y-C Out
Subaddress
Setting
0x17
0x02
0x00
0x1C
0x01
0x00
0x80
0x10
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/S-Video out. SSAF
PrPb filter enabled. Active video edge
control enabled. Pedestal enabled.
RGB input enabled.
16-bit input enabled.
Timing Mode 2 (Slave). HSYNC/VSYNC
synchronization.
0x82
0xCB
0x87
0x88
0x8A
0x80
0x08
0x0C
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