參數(shù)資料
型號(hào)： ADV7393EBZ
廠商： Analog Devices, Inc.
英文描述： Low Power, Chip Scale 10-Bit SD/HD Video Encoder
中文描述： 低功耗，芯片尺寸10位標(biāo)清/高清視頻編碼器
文件頁數(shù)： 60/96頁
文件大?。?/td> 1209K
代理商： ADV7393EBZ
ADV7390/ADV7391/ADV7392/ADV7393
EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For timing synchronization purposes, the ADV739x is able to accept either EAV/SAV time codes embedded in the input pixel data or
external synchronization signals provided on the HSYNC and VSYNC pins (see Table 48). It is also possible to output synchronization
signals on the HSYNC and VSYNC pins (see Table 49 to Table 51).
Rev. 0 | Page 61 of 96
Table 48. Timing Synchronization Signal Input Options
Signal
Pin
SD HSYNC In
HSYNC
SD VSYNC/FIELD In
VSYNC
ED/HD HSYNC In
HSYNC
ED/HD VSYNC/FIELD In
VSYNC
Condition
SD Slave Timing Mode 1, Mode 2, or Mode 3 Selected (Subaddress 0x8A[2:0]).
1
SD Slave Timing Mode 1, Mode 2, or Mode 3 Selected (Subaddress 0x8A[2:0]).
1
ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).
ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).
1
SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).
Table 49. Timing Synchronization Signal Output Options
Signal
Pin
SD HSYNC Out
HSYNC
SD VSYNC/FIELD Out
VSYNC
ED/HD HSYNC Out
HSYNC
ED/HD VSYNC/FIELD Out
VSYNC
Condition
SD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 6 = 1).
1
SD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 6 = 1).
1
ED/HD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 7 = 1).
2
ED/HD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 7 = 1).
2
1
ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).
2
ED/HD timing synchronization inputs must also be disabled, that is, embedded EAV/SAV timing codes must be enabled (Subaddress 0x30, Bit 2 = 1).
Table 50. HSYNC Output Control
1
ED/HD Input Sync
Format (0x30, Bit 2)
x
x
ED/HD HSYNC
Control
(0x34, Bit 1)
x
x
ED/HD Sync
Output Enable
(0x02, Bit 7)
0
0
SD Sync
Output Enable
(0x02, Bit 6)
0
1
Signal on HSYNC Pin
Tristate.
Pipelined SD HSYNC.
Duration
–
See
Error! Reference
source not found.
.
As per HSYNC timing.
Same as line blanking
interval.
Same as embedded
HSYNC.
0
1
0
0
1
1
x
x
Pipelined ED/HD HSYNC.
Pipelined ED/HD HSYNC based on
AV Code H bit.
Pipelined ED/HD HSYNC based on
horizontal counter.
x
1
1
x
1
In all ED/HD standards where there is a HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
Table 51. VSYNC Output Control
1
ED/HD Input
Sync Format
(0x30, Bit 2)
(0x34, Bit 2)
x
x
x
x
ED/HD VSYNC
Control
ED/HD Sync
Output Enable
(0x02, Bit 7)
0
0
SD Sync
Output Enable
(0x02, Bit 6)
0
1
Video Standard
x
Interlaced
Signal on VSYNC Pin
Tristate.
Pipelined SD VSYNC/Field.
Duration
–
See
Error!
Reference source
not found.
.
As per VSYNC or
Field signal timing.
Field.
0
0
1
x
x
Pipelined ED/HD VSYNC
or field signal.
Pipelined Field signal
based on AV Code F bit.
Pipelined VSYNC based on
AV Code V bit.
Pipelined ED/HD VSYNC
based on vertical counter.
Pipelined ED/HD VSYNC
based on vertical counter.
1
0
1
x
All HD interlaced
standards
All ED/HD progressive
standards
All ED/HD standards
except 525p
525p
1
0
1
x
Vertical blanking
interval.
Aligned with
serration lines.
Vertical blanking
interval.
x
1
1
x
x
1
1
x
1
In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video.
相關(guān)PDF資料
PDF描述
ADV7400AKSTZ-80 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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ADV73946604 制造商:LG Corporation 功能描述:Frame Assembly
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