參數(shù)資料
型號(hào)： ADV7393EBZ
廠(chǎng)商： Analog Devices, Inc.
英文描述： Low Power, Chip Scale 10-Bit SD/HD Video Encoder
中文描述： 低功耗，芯片尺寸10位標(biāo)清/高清視頻編碼器
文件頁(yè)數(shù)： 45/96頁(yè)
文件大小： 1209K
代理商： ADV7393EBZ
ADV7390/ADV7391/ADV7392/ADV7393
FEATURES
OUTPUT OVERSAMPLING
The ADV739x include an on-chip phase-locked loop (PLL) that
allows for oversampling of SD, ED, and HD video data. By
default, the PLL is disabled. The PLL can be enabled using
Subaddress 0x00, Bit 1 = 0.
Table 35 shows the various oversampling rates supported in the
ADV739x.
ED/HD NONSTANDARD TIMING MODE
Subaddress 0x30, Bits[7:3] = 00001
For any ED/HD input data that does not conform to
the standards listed in the ED/HD input mode table
(Subaddress 0x30, Bits[7:3]), the ED/HD nonstandard
timing mode can be used to interface to the ADV739x.
ED/HD nonstandard timing mode can be enabled by
setting Subaddress 0x30, Bits[7:3] to 00001.
A clock signal must be provided on the CLKIN pin. HSYNC
and VSYNC must be toggled by the user to generate the
appropriate horizontal and vertical synchronization pulses on
the analog output from the encoder. Figure 61 illustrates the
Rev. 0 | Page 45 of 96
various output levels that can be generated. Table 36 lists the
transitions required to generate the various output levels.
Embedded EAV/SAV timing codes are not supported in
ED/HD nonstandard timing mode.
The user must ensure that appropriate pixel data is applied to
the encoder where the blanking level is expected at the output.
Macrovision (ADV7390/ADV7392 only) and output
oversampling are not available in ED/HD nonstandard timing
mode. The PLL must be disabled (Subaddress 0x00, Bit 1 = 1) in
ED/HD nonstandard timing mode.
ACTIVE VIDEO
ANALOG
a
b
c
b
b
a = TRI-LEVEL SYNCHRONIZATION PULSE LEVEL.
b = BLANKING LEVEL/ACTIVE VIDEO LEVEL.
BLANKING LEVEL
0
Figure 61. ED/HD Nonstandard Timing Mode Output Levels
Table 35. Output Oversampling Modes and Rates
Input Mode
(0x01, Bits[6:4])
000
SD
000
SD
000
SD
001/010
ED
001/010
ED
001/010
ED
001/010
HD
001/010
HD
001/010
HD
111
ED (at 54 MHz)
111
ED (at 54 MHz)
111
ED (at 54 MHz)
PLL and Oversampling
Control (0x00, Bit 1)
1
0
0
1
0
0
1
0
0
1
0
0
SD/ED Oversample Rate
Select (0x0D, Bit 3)
x
1
0
x
1
0
x
x
x
x
1
0
HD Oversample Rate
Select (0x31, Bit 1)
x
x
x
x
x
x
x
1
0
x
x
x
Oversampling Mode
and Rate
SD (2×)
SD (8×)
SD (16×)
ED (1×)
ED (4×)
ED (8×)
HD (1×)
HD (2×)
HD (4×)
ED (@ 54 MHz) (1×)
ED (@ 54 MHz) (4×)
ED (@ 54 MHz) (8×)
Table 36. ED/HD Nonstandard Timing Mode Synchronization Signal Generation
Output Level Transition
1
b
→
c
c
→
a
a
→
b
c
→
b
1
a = Tri-level synchronization pulse level; b = blanking level/active video level; c = synchronization pulse level. See Figure 61.
2
If VSYNC = 1, it should transition to 0. If VSYNC = 0, it should remain at 0. If tri-level synchronization pulse generation is not required, VSYNC should always be 0.
HSYNC
1
→
0
0
0
→
1
0
→
1
VSYNC
1
→
0 or 0
2
0
→
1
1
0
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參數(shù)描述
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