參數(shù)資料
型號(hào)： ADV7188
廠(chǎng)商： Analog Devices, Inc.
英文描述： Multiformat SDTV Video Decoder with Fast Switch Overlay Support
中文描述： 標(biāo)清多格式視頻解碼器支持快速開(kāi)關(guān)重疊
文件頁(yè)數(shù)： 73/112頁(yè)
文件大?。?/td> 943K
代理商： ADV7188
ADV7188
MPU PORT DESCRIPTION
The ADV7188 supports a 2-wire (I
2
C-compatible) serial inter-
face. Two inputs, serial data (SDA) and serial clock (SCLK),
carry information between the ADV7188 and the system I
2
C
master controller. Each slave device is recognized by a unique
address. The ADV7188’s I
2
C port allows the user to set up and
configure the decoder and to read back captured VBI data. The
ADV7188 has four possible slave addresses for both read and
write operations, depending on the logic level on the ALSB pin.
These four unique addresses are shown in Table 99. The
ADV7188’s ALSB pin controls Bit 1 of the slave address. By
altering the ALSB, it is possible to control two ADV7188s in an
application without having a conflict with the same slave
address. The LSB (Bit 0) sets either a read or write operation.
Logic 1 corresponds to a read operation; Logic 0 corresponds to
a write operation.
Table 99. I
2
C Address
ALSB
R/W
Slave Address
0
0
0x40
0
1
0x41
1
0
0x42
1
1
0x43
To control the device on the bus, a specific protocol must be
followed. First, the master initiates a data transfer by
establishing a start condition, which is defined by a high-to-low
transition on SDA while SCLK remains high. This indicates that
an address/data stream follows. All peripherals respond to the
start condition and shift the next eight bits (7-bit address +
R/W bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse; this is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDA and SCLK
lines, waiting for the start condition and the correct transmitted
address.
Rev. 0 | Page 73 of 112
The R/W bit determines the direction of the data. Logic 0 on
the LSB of the first byte means the master writes information to
the peripheral. Logic 1 on the LSB of the first byte means the
master reads information from the peripheral.
The ADV7188 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses plus the R/W bit. The ADV7188 has 249 subaddresses
to enable access to the internal registers. It therefore interprets
the first byte as the device address and the second byte as the
starting subaddress. The subaddresses auto-increment, allowing
data to be written to or read from the starting subaddress. A
data transfer is always terminated by a stop condition. The user
can also access any unique subaddress register on a one-by-one
basis without updating all the registers.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLK high period,
the user should issue only one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADV7188 does
not issue an acknowledge and returns to the idle condition.
If in autoincrement mode the highest subaddress is exceeded,
the following action is taken:
1.
In read mode, the highest subaddress register contents
continue to be output until the master device issues a no
acknowledge. This indicates the end of a read. In a no
acknowledge condition, the SDA line is not pulled low on
the ninth pulse.
2.
In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by
the ADV7188, and the part returns to the idle condition.
0
SDATA
SCLOCK
START ADDR
ACK
ACK
DATA
ACK
STOP
SUBADDRESS
1–7
1–7
8
9
8
9
1–7
8
9
S
P
R/W
Figure 44. Bus Data Transfer
0
S
WRITE
SEQUENCE
SLAVE ADDR
A(S)
SUB ADDR
A(S)
DATA
A(S)
DATA
A(S)
P
S
READ
SEQUENCE
SLAVE ADDR
SLAVE ADDR
A(S)
SUB ADDR
A(S) S
A(S)
DATA
A(M)
DATA
A(M) P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
LSB = 1
LSB = 0
Figure 45. Read and Write Sequence
相關(guān)PDF資料
PDF描述
ADV7189B Multiformat SDTV Video Decoder
ADV7189BBSTZ268H Multiformat SDTV Video Decoder
ADV7189BKSTZ10F Multiformat SDTV Video Decoder
ADV7189 Multiformat SDTV Video Decoder
ADV7189KST Multiformat SDTV Video Decoder
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7188BSTZ 功能描述:IC DECODER VID MULTIFORM 80LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類(lèi)型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱(chēng):Q4645799
ADV7189 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Multiformat SDTV Video Decoder
ADV7189B 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Multiformat SDTV Video Decoder
ADV7189BBSTZ 功能描述:IC VIDEO DECODER SDTV 80-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類(lèi)型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱(chēng):Q4645799
ADV7189BBSTZ268H 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Multiformat SDTV Video Decoder
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