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ADV7188
AD_N443_EN Enable Autodetection of NTSC 443,
Address 0x07 [5]
0—Disables the autodetection of NTSC style systems with a
4.43 MHz color subcarrier.
1 (default)—Enables autodetection.
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AD_P60_EN Enable Autodetection of PAL-60,
Address 0x07 [4]
0—Disables the autodetection of PAL systems with a 60 Hz
field rate.
1 (default)—Enables autodetection.
AD_PALN_EN Enable Autodetection of PAL-N,
Address 0x07 [3]
0—Disables the autodetection of the PAL -N standard.
1 (default)—Enables autodetection.
AD_PALM_EN Enable Autodetection of PAL-M,
Address 0x07 [2]
0—Disables the autodetection of PAL-M.
1 (default)—Enables autodetection.
AD_NTSC_EN Enable Autodetection of NTSC,
Address 0x07 [1]
0—Disables the autodetection of standard NTSC.
1 (default)—Enables autodetection.
AD_PAL_EN Enable Autodetection of PAL,
Address 0x07 [0]
0—Disables the autodetection of standard PAL.
1 (default)—Enables autodetection.
Subcarrier Frequency Lock Inversion
The SFL_INV bit controls the behavior of the PAL switch bit in
the SFL (GenLock Telegram) data stream. It was implemented
to solve some compatibility issues with video encoders. It solves
two problems.
First, the PAL switch bit is only meaningful in PAL. Some
encoders (including Analog Devices encoders) also look at the
state of this bit in NTSC.
Second, there was a design change in Analog Devices encoders
from ADV717x to ADV719x. The older versions used the SFL
(GenLock Telegram) bit directly, while the later ones invert the
bit prior to using it. The reason for this is that the inversion
compensated for the 1-line delay of an SFL (GenLock Telegram)
transmission.
As a result, ADV717x encoders need the PAL switch bit in the
SFL (GenLock Telegram) to be 1 for NTSC to work. Also, the
ADV7190/ADV7191/ADV7194 encoders need the PAL switch
bit in the SFL to be 0 to work in NTSC. If the state of the PAL
switch bit is wrong, a 180°phase shift occurs.
In a decoder/encoder back-to-back system in which SFL is used,
this bit must be set up properly for the specific encoder used.
SFL_INV Address 0x41 [6]
0 (default)—Makes the part SFL-compatible with ADV7190/
ADV7191/ADV7194 and ADV73xx encoders.
1—Makes the part SFL-compatible with ADV717x encoders.
Lock-Related Controls
Lock information is presented to the user through Bits [1:0] of
the Status 1 register. See the STATUS_1[7:0] Address 0x10 [7:0]
section. Figure 13 outlines the signal flow and the controls
available to influence the way the lock status information is
generated.
SRLS Select Raw Lock Signal, Address 0x51 [6]
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits [1:0] in the Status 1
register).
The time_win signal is based on a line-to-line evaluation of the
horizontal synchronization pulse of the incoming video. It reacts
quite quickly.
The free_run signal evaluates the properties of the incoming
video over several fields, and takes vertical synchronization
information into account.
0 (default)—Selects the free_run signal.
1—Selects the time_win signal.
0
1
0
TIME_WIN
FREE_RUN
STATUS 1 [0]
SELECT THE RAW LOCK SIGNAL
SRLS
FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]
TAKE F
SC
LOCK INTO ACCOUNT
FSCLE
STATUS 1 [1]
F
SC
LOCK
1
0
COUNTER INTO LOCK
COUNTER OUT OF LOCK
MEMORY
Figure 13. Lock-Related Signal Path