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參數(shù)資料
| 型號： | ADV7188 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SDTV Video Decoder with Fast Switch Overlay Support |
| 中文描述： | 標清多格式視頻解碼器支持快速開關重疊 |
| 文件頁數(shù)： | 72/112頁 |
| 文件大?。?/td> | 943K |
| 代理商： | ADV7188 |
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ADV7188
PIXEL PORT CONFIGURATION
The ADV7188 has a very flexible pixel port that can be config-
ured in a variety of formats to accommodate downstream ICs.
Table 97 and Table 98 summarize the various functions that the
ADV7188 pins can have in different modes of operation.
Rev. 0 | Page 72 of 112
The ordering of components, for example, Cr vs. Cb, CHA/B/C,
can be changed. Refer to the SWPC Swap Pixel Cr/Cb, Address
0x27 [7] section. Table 97 indicates the default positions for the
Cr/Cb components.
OF_SEL[3:0] Output Format Selection, Address 0x03 [5:2]
The modes in which the ADV7188 pixel port can be configured
are under the control of OF_SEL[3:0]. See Table 98 for details.
The default LLC frequency output on the LLC1 pin is approxi-
mately 27 MHz. For modes that operate with a nominal data
rate of 13.5 MHz (0001, 0010), the clock frequency on the LLC1
pin stays at the higher rate of 27 MHz. For information on
outputting the nominal 13.5 MHz clock on the LLC1 pin, see
the LLC_PAD_SEL[2:0] LLC1 Output Selection, Address 0x8F
[6:4] section.
Table 97. P19–P0 Output/Input Pin Mapping
SWPC Swap Pixel Cr/Cb, Address 0x27 [7]
0 (default)—No swapping is allowed.
1—The Cr and Cb values can be swapped.
LLC_PAD_SEL[2:0] LLC1 Output Selection, Address 0x8F [6:4]
The following I
2
C write allows the user to select between LLC1
(nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).
The LLC2 signal is useful for LLC2-compatible wide bus (16-/20-
bit) output modes. See the OF_SEL[3:0] Output Format Selection,
Address 0x03 [5:2] section for additional information. The LLC2
signal and data on the data bus are synchronized. By default, the
rising edge of LLC1/LLC2 is aligned with the Y data; the falling
edge occurs when the data bus holds C data. The polarity of the
clock, and therefore the Y/C assignments to the clock edges, can be
altered by using the Polarity LLC pin.
000 (default)—The output is nominally 27 MHz LLC on the
LLC1 pin.
101—The output is nominally 13.5 MHz LLC on the LLC1 pin.
Data Port Pins P[19:0]
12
11
Processor, Format, and Mode
Video Out, 8-Bit, 4:2:2
Video Out, 10-Bit, 4:2:2
Video Out, 16-Bit, 4:2:2
Video Out, 20-Bit, 4:2:2
Table 98. Standard Definition Pixel Port Modes
OF_SEL[3:0]
0000
0001
0010
0011 (default)
0110-1111
19
18
17
16
15
14
13
10
9
8
7
CrCb[7:0] OUT
CrCb[9:0] OUT
6
5
4
3
2
1
0
YCrCb[7:0]OUT
YCrCb[9:0]OUT
Y[7:0]OUT
Y[9:0]OUT
Format
10-Bit at LLC1 4:2:2
20-Bit at LLC2 4:2:2
16-Bit at LLC2 4:2:2
8-Bit at LLC1 4:2:2
Reserved
Pixel Port Pins P[19:0]
P[19:10]
P9[9:0]
P[19:12]
YCrCb[9:2]
Y[9:2]
Y[7:0]
YCrCb[7:0]
P[11:10]
YCrCb[1:0]
Y[1:0]
Three-State
Three-State
P[9:2]
Three-State
CrCb[9:2]
CrCb[7:0]
Three-State
P[1:0]
Three-State
CrCb[1:0]
Three-State
Three-State
Reserved. Do not use.
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PDF描述 |
|---|---|
| ADV7189B | Multiformat SDTV Video Decoder |
| ADV7189BBSTZ268H | Multiformat SDTV Video Decoder |
| ADV7189BKSTZ10F | Multiformat SDTV Video Decoder |
| ADV7189 | Multiformat SDTV Video Decoder |
| ADV7189KST | Multiformat SDTV Video Decoder |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7188BSTZ | 功能描述:IC DECODER VID MULTIFORM 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7189 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189B | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189BBSTZ | 功能描述:IC VIDEO DECODER SDTV 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7189BBSTZ268H | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
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