參數(shù)資料
型號(hào): ADV7188
廠商: Analog Devices, Inc.
英文描述: Multiformat SDTV Video Decoder with Fast Switch Overlay Support
中文描述: 標(biāo)清多格式視頻解碼器支持快速開(kāi)關(guān)重疊
文件頁(yè)數(shù): 70/112頁(yè)
文件大?。?/td> 943K
代理商: ADV7188
ADV7188
LB_TH[4:0] Letterbox Threshold Control, Address 0xDC [4:0]
Table 93. LB_TH Function
LB_TH[4:0]
Description
01100
(default)
01101 to
10000
content before identifying nonblack lines).
00000 to
01011
cause the detection of nonblack lines).
LB_SL [3:0] Letterbox Start Line, Address 0xDD [7:4]
The LB_SL[3:0] bits are set at 0100 by default. For an NTSC
signal this window is from Line 23 to Line 286.
Rev. 0 | Page 70 of 112
Default threshold for detection of black lines.
Increase threshold (need larger active video
Decrease threshold (even small noise levels can
By changing the bits to 0101, the detection window starts on
Line 24 and ends on Line 287.
LB_EL[3:0] Letterbox End Line, Address 0xDD [3:0]
The LB_EL[3:0] bits are set at 1101 by default. This means that
letterbox detection window ends with the last active video line.
For an NTSC signal, this window is from Line 262 to Line 525.
By changing the bits to 1100, the detection window starts on
Line 261 and ends on Line 254.
IF Compensation Filter
IFFILTSEL[2:0] IF Filter Select Address 0xF8 [2:0]
The IFFILTSEL[2:0] register allows the user to compensate for
SAW filter characteristics on a composite input as would be
observed on tuner outputs. Figure 42 and Figure 43 show IF
filter compensation for NTSC and PAL.
The options for this feature are as follows:
Bypass mode (default)
NTSC—consists of three filter characteristics
PAL—consists of three filter characteristics
0
FREQUENCY (MHz)
2.0
4.0
3.5
3.0
2.5
5.0
4.5
–12
–10
–8
–6
–4
–2
0
2
4
6
A
Figure 42. NTSC IF Compensation Filter Responses
0
FREQUENCY (MHz)
3.0
5.0
4.5
4.0
3.5
6.0
5.5
–8
–6
–4
–2
0
2
4
6
A
Figure 43. PAL IF Compensation Filter Responses
See Table 101 for programming details.
I
2
C Interrupt System
The ADV7188 has a comprehensive interrupt register set. This
map is located in the User Sub Map. See Table 103 for details of
the interrupt register map. Figure 46. describes how to access
this map.
Interrupt Request Output Operation
When an interrupt event occurs, the interrupt pin INTRQ
goes low with a programmable duration given by
INTRQ_DUR_SEL[1:0]
INTRQ_DURSEL[1:0], Interrupt Duration Select
Address 0x40 [7:6] (User Sub Map)
Table 94. INTRQ_DUR_SEL
INTRQ_DURSEL[1:0]
Description
00 (default)
3 XTAL periods.
01
15 XTAL periods.
10
63 XTAL periods.
11
Active until cleared.
When the active-until-cleared interrupt duration is selected,
and the event that caused the interrupt is no longer in force, the
interrupt persists until it is masked or cleared.
For example, if the ADV7188 loses lock, an interrupt is generated
and the INTRQ pin goes low. If the ADV7188 returns to the
locked state, INTRQ
continues to drive low until the SD_LOCK
bit is either masked or cleared.
Interrupt Drive Level
The ADV7188 resets with open drain enabled and all interrupts
masked off. Therefore INTRQ is in a high impedance state after
reset. 01 or 10 has to be written to INTRQ_OP_SEL[1:0] for a
logic level to be driven out from the INTRQ pin.
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