參數(shù)資料
型號(hào): ADV7184BSTZ
廠商: ANALOG DEVICES INC
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: Multiformat SDTV Video Decoder with Fast Switch Overlay Support
中文描述: COLOR SIGNAL DECODER, PQFP80
封裝: LEAD FREE, MS-026BEC, LQFP-80
文件頁數(shù): 78/108頁
文件大?。?/td> 925K
代理商: ADV7184BSTZ
ADV7184
Address
0x0A
Rev. 0 | Page 78 of 108
Register
Brightness Register
Bit Description
BRI[7:0]. This register controls the
brightness of the video signal.
Bit
Notes
0x00 = 0mV
0x7F = +204mV
0x80 = -204mV
Hue range =–90° to +90°
7 6 5 4 3 2
0 0 0 0 0 0
1 0 Comments
0
0
0x0B
Hue Register
HUE[7:0]. This register contains the value for
the color hue adjustment.
DEF_VAL_EN. Default value enable.
0 0 0 0 0 0
0
0
0 Free-run mode dependent on
DEF_VAL_AUTO_EN
1 Force free-run mode on and output
blue screen
Disable free-run mode
Enable automatic free-run mode
(blue screen)
0
1
DEF_VAL_AUTO_EN. Default value.
When lock is lost, free-run
mode can be enabled to
output stable timing, clock,
and a set color.
Default Y value output in free-
run mode.
0 0 1 1 0 1
0 1 1 1 1 1
0
0
0x0C
Default Value Y
DEF_Y[5:0]. Default value Y. This register
holds the Y default value.
Y[7:0] = {DEF_Y[5:0],0, 0}
0x0D
Default Value C
DEF_C[7:0]. Default value C. The Cr and Cb
default values are defined in this register.
Cr[7:0] = DEF_C[7:4],0, 0, 0, 0}
Cb[7:0] = DEF_C[3:0], 0, 0, 0, 0}
Default Cb/Cr value output in
free-run mode. Default values
give blue screen output.
See Figure 46.
Reserved..
SUB_USR_EN. Enables the user to access
the User Sub Map
0 0
0
0
1
0
1
0 0 0
0 0
0
1
0
0
1
0 Set as default
Access User Map
Access User Sub Map
Set as default
0 Set to default
FB input operational
FB input in power save mode
Chip power-down controlled by pin
Bit has priority (pin disregarded)
Set to default
System functional
Powered down
Set to default
Normal operation
Start reset sequence
0
1
0x0E
ADI Control
Reserved.
Reserved.
FB_PWRDN
PDBP. Power-down bit priority selects
between PWRDN bit or pin.
See PDBP, 0x0F Bit 2.
Executing reset takes approx.
2 ms. Self-clearing.
Provides information about
the internal status of the
decoder.
Reserved.
PWRDN. Power-down places the decoder in
a full power-down mode.
Reserved.
RES. Chip Reset loads all I
2
C bits with default
values.
0x0F
Power Management
IN_LOCK
LOST_LOCK
FSC_LOCK
FOLLOW_PW
AD_RESULT[2:0]. Autodetection result
reports the standard of the Input video.
x
x x
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
x
x
x
x
x
x
x In lock (right now) = 1
Lost lock (since last read) = 1
Fsc lock (right now) = 1
Peak white AGC mode active = 1
NTSM-MJ
NTSC-443
PAL-M
PAL-60
PAL-BGHID
SECAM
PAL combination N
SECAM 525
Color kill is active = 1
x MV color striping detected
MV color striping type
MV pseudo Sync detected
MV AGC pulses detected
Nonstandard line length
Fsc frequency nonstandard
x 1 = horizontal lock achieved
1 = Gemstar Data detected
x
Detected standard
0x10
Status Register 1
(Read Only)
COL_KILL
MVCS DET
MVCS T3
MV_PS DET
MV_AGC DET
LL_NSTD
FSC_NSTD
Reserved.
INST_HLOCK
GEMD
x
x
Color Kill
1 = Detected
0 = Type 2; 1 = Type 3
1 = Detected
1 = Detected
1 = Detected
1 = Detected
Unfiltered
When GEMD bit goes HIGH, it
will remain HIGH until end of
active video lines in that field.
0 = SD 60 Hz detected;
1 = SD 50 Hz detected.
0 = Y/C; 1 = CVBS
Blue screen output
Correct field length found
Field sequence found
0x12
Status Register 2
(Read Only)
SD_OP_50HZ
x
SD field rate detect
CVBS
FREE_RUN_ACT
STD FLD_LEN
INTERLACED
x
x
x
x
Result of CVBS/YC autodetection
1 = Free-run mode active
1 = Field length standard
1 = Interlaced video detected
0x13
Status Register 3
(Read only)
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