參數(shù)資料
型號(hào)： ADV7184BSTZ
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Multiformat SDTV Video Decoder with Fast Switch Overlay Support
中文描述： COLOR SIGNAL DECODER, PQFP80
封裝： LEAD FREE, MS-026BEC, LQFP-80
文件頁數(shù)： 70/108頁
文件大?。?/td> 925K
代理商： ADV7184BSTZ
ADV7184
Interrupt Drive Level
Rev. 0 | Page 70 of 108
The ADV7184 resets with open drain enabled and all interrupts
masked off. Therefore INTRQ is in a high impedance state after
reset. 01 or 10 has to be written to INTRQ_OP_SEL[1:0] for a
logic level to be driven out from the INTRQ pin.
It is also possible to write to a register in the ADV7184 that
manually asserts the INTRQ pin. This bit is MPU_STIM_INTRQ.
INTRQ_OP_SEL[1:0], Interrupt Duration Select
Address 0x40 [1:0], User Sub Map
Table 96. INTRQ_OP_SEL
INTRQ_OP_SEL[1:0]
Description
00 (default)
Open drain.
01
Drive low when active.
10
Drive high when active.
11
Reserved.
Multiple Interrupt Events
If interrupt event 1 occurs and then interrupt event 2 occurs
before the system controller has cleared or masked interrupt
event 1, the ADV7184 does not generate a second interrupt
signal. The system controller should check all unmasked
interrupt status bits since more than one may be active.
Macrovision Interrupt Selection Bits
The user can select between pseudo sync pulse and color stripe
detection as follows:
MV_INTRQ_SEL[1:0], Macrovision Interrupt Selection Bits
Address 0x40 [5:4], User Sub Map
Table 97. MV_INTRQ_SEL
MV_INTRQ_SEL
[1:0]
Description
00
Reserved.
01 (default)
Pseudo sync only.
10
Color stripe only.
11
Either pseudo sync or color stripe.
Additional information relating to the interrupt system is
detailed in Table 104.
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