參數(shù)資料
型號： ADV7184BSTZ
廠商： ANALOG DEVICES INC
元件分類： 顏色信號轉(zhuǎn)換
英文描述： Multiformat SDTV Video Decoder with Fast Switch Overlay Support
中文描述： COLOR SIGNAL DECODER, PQFP80
封裝： LEAD FREE, MS-026BEC, LQFP-80
文件頁數(shù)： 59/108頁
文件大?。?/td> 925K
代理商： ADV7184BSTZ
ADV7184
Table 76. CGMS Readback Registers
1
Signal Name
CGMS_WSS_DATA_0[3:0]
CGMS_WSS_DATA_1[7:0]
CGMS_WSS_DATA_2[7:0]
Rev. 0 | Page 59 of 108
Register Location
VDP_CGMS_WSS_DATA_0 [3:0]
VDP_CGMS_WSS_DATA_1 [7:0]
VDP_CGMS_WSS_DATA_2 [7:0]
Address (User Sub Map)
125
126
127
0x7D
0x7E
0x7F
1
The register is a readback register; default value does not apply.
0
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = F
= 3.579545MHz
AMPLITUDE = 40 IRE
10.003
μ
s
1
(O7 CYCLES
2 3 4 5 6 7 0 1 2 3 4 5 6 7
P
A
R
I
T
Y
S
T
A
R
T
P
A
R
I
T
Y
VDP_CCAP_DATA_0
33.764
μ
s
10.5
±
0.25
μ
s
12.91
μ
s
27.382
μ
s
50 IRE
40 IRE
0
VDP_CCAP_DATA_1
Figure 39.CCAP Waveform and Decoded Data Correlation
Table 77. CCAP Readback Registers
1
Signal Name
CCAP_BYTE_1[7:0]
CCAP_BYTE_2[7:0]
Register Location
VDP_CCAP_DATA_0[7:0]
VDP_CCAP_DATA_1[7:0]
Address (User Sub Map)
121
122
0x79
0x7A
1
The register is a readback register; default value does not apply.
BIT0, BIT1
BIT88, BIT89
TO
VITC WAVEFORM
0
Figure 40. VITC Waveform and Decoded Data Correlation
VITC
VITC has a sync sequence of 10 in between each data byte.
The VDP strips these syncs from the data stream to give out
only the data bytes. The VITC results are available in
VDP_VITC_DATA_0 to VDP_VITC_DATA_8 registers
(Register 0x92 to Register 0x9A, User Sub Map).
The VITC has a CRC byte at the end; the in-between syncs
are also used in this CRC calculation. Since the in-between
syncs are not given out, the CRC is also calculated internally.
The calculated CRC is also available for the user in
VITC_CALC_CRC
register (Resister 0x9B, User Sub Map).
Once the VDP completes decoding the VITC line, the
VITC_DATA and VITC_CALC_CRC registers are updated
and VITC_AVL bit is set.
VITC_CLEAR VITC Clear, Address 0x78 [6], User Sub Map,
Write Only, Self Clearing
1—Re-initializes the VITC readback registers.
VITC_AVL VITC Available, Address 0x78 [6], User Sub Map
0—VITC data was not detected.
1—VITC data was detected.
VITC Readback Registers
See Figure 40 for the I
2
C to VITC bit mapping.
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