參數(shù)資料
型號(hào): ADV7184BSTZ
廠商: ANALOG DEVICES INC
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: Multiformat SDTV Video Decoder with Fast Switch Overlay Support
中文描述: COLOR SIGNAL DECODER, PQFP80
封裝: LEAD FREE, MS-026BEC, LQFP-80
文件頁數(shù): 45/108頁
文件大?。?/td> 925K
代理商: ADV7184BSTZ
ADV7184
NFTOGDELO NTSC Field Toggle Delay on Odd Field,
Address 0xE7 [7]
0 (default)—No delay.
1—Delays the field toggle/transition on an odd field by a line
relative to NFTOG.
Rev. 0 | Page 45 of 108
NFTOGDELE NTSC Field Toggle Delay on Even Field,
Address 0xE7 [6]
0—No delay.
1 (default)—Delays the field toggle/transition on an even field
by a line relative to NFTOG.
0
ADVANCE TOGGLE OF
FIELD BY NFTOG[4:0]
DELAY TOGGLE OF
FIELD BY NFTOG[4:0]
NFTOGSIGN
ODD FIELD
0
1
NO
YES
NFTOGDELE
ADDITIONAL
DELAY BY
1 LINE
1
0
NFTOGDELO
ADDITIONAL
DELAY BY
1 LINE
1
0
FIELD
TOGGLE
NOT VALID FOR USER
PROGRAMMING
Figure 31. NTSC FIELD Toggle
NFTOGSIGN NTSC Field Toggle Sign, Address 0xE7 [5]
0—Delays the field transition. Set for user manual
programming.
1 (default)—Advances the field transition. Not recommended
for user programming.
NFTOG[4:0] NTSC Field Toggle, Address 0xE7 [4:0]
The default value of NFTOG is 00011, indicating the NTSC
Field toggle position.
For all NTSC/PAL field timing controls, both the F bit in the
AV code and the field signal on the FIELD/DE pin are modified.
PVBEGDELO PAL VSYNC Begin Delay on Odd Field,
Address 0xE8 [7]
0 (default)—No delay.
1—Delays VSYNC going high on an odd field by a line relative
to PVBEG.
PVBEGDELE PAL VSYNC Begin Delay on Even Field,
Address 0xE8 [6]
0 (default)—No delay.
1 (default)—Delays VSYNC going high on an even field by a
line relative to PVBEG.
PVBEGSIGN PAL VSYNC Begin Sign, Address 0xE8 [5]
0—Delays the beginning of VSYNC. Set for user manual
programming.
1 (default)—Advances the beginning of VSYNC. Not
recommended for user programming.
PVBEG[4:0] PAL VSYNC Begin, Address 0xE8 [4:0]
The default value of PVBEG is 00101, indicating the PAL
VSYNC begin position.
For all NTSC/PAL VSYNC timing controls, both the V bit in
the AV code and the VSYNC on the VS pin are modified.
Table 63. Recommended User Settings for PAL (see Figure 33)
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0xE8
0xE9
0xEA
Register Name
VSYNC Field Control 1
VSYNC Field Control 2
VSYNC Field Control 3
HSYNC Position 1
HSYNC Position 2
HSYNC Position 3
Polarity
PAL_V_Bit_Beg
PAL_V_Bit_End
PAL_F_Bit_Tog
Write
0x1A
0x81
0x84
0x00
0x00
0x7D
0xA1
0x41
0x84
0x06
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