參數(shù)資料
型號(hào)： ADSP-21371BSWZ-2B
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/48頁(yè)
文件大?。?/td> 0K
描述： IC DSP 32BIT 266MHZ 208-LQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： DAI，DPI
時(shí)鐘速率： 266MHz
非易失內(nèi)存： ROM（512 kB）
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 208-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 208-LQFP-EP（28x28）
包裝： 托盤(pán)
ADSP-21371
Table 5. Pin List (Continued)
Name
Type
State During
and After Reset Description
FLAG[0]/IRQ0
I/O
High-Z/high-Z
FLAG0/Interrupt Request0.
FLAG[1]/IRQ1
I/O
High-Z/high-Z
FLAG1/Interrupt Request1.
FLAG[2]/IRQ2/
MS2
I/O with
programmable pu
(for MS mode)
High-Z/high-Z
FLAG2/Interrupt Request/Memory Select2.
FLAG[3]/TIMEXP/M
S3
I/O with
programmable pu
(for MS mode)
High-Z/high-Z
FLAG3/Timer Expired/Memory Select3.
TDI
I (pu)
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 k
Ω internal pull-up resistor.
TDO
O /T
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TMS
I (pu)
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 k
Ω
internal pull-up resistor.
TCK
I
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed
low) after power-up or held low for proper operation of the ADSP-21371.
TRST
I (pu)
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the ADSP-21371. TRST has a 22.5 k
Ω internal
pull-up resistor.
EMU
O/T (pu)
Emulation Status. Must be connected to the ADSP-21371 Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU has a 22.5 k
Ω internal
pull-up resistor.
CLK_CFG1–0
I
Core to CLKIN Ratio Control. These pins set the start up clock frequency. See Table 8 for
a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.
BOOT_CFG1–0
I
Boot Configuration Select. These pins select the boot mode for the processor. The
BOOTCFG pins must be valid before reset is asserted. See Table 7 for a description of the
boot modes.
RESET
I
Processor Reset. Resets the ADSP-21371 to a known state. Upon deassertion, there is a
4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted (low)
at power-up.
XTAL
O
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.
CLKIN
I
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21371 clock input. It
configures the ADSP-21371 to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected
configures the ADSP-21371 to use the external clock source such as an external clock
oscillator. CLKIN may not be halted, changed, or operated below the specified frequency.
CLKOUT/
RESETOUT/
RUNRSTIN
I/O (pu)
Clock Out/Reset Out/Running Reset In. The functionality can be switched between the
PLL output clock and reset out by setting Bit 12 of the PMCTREG register. The default is
reset out. This pin also has a third function as RUNRSTIN. The functionality of which is
enabled by setting bit 0 of the RUNRSTCTL register. For more information, see the
ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21367/8/9 Processors.
1 Pull-up can be enabled/disabled, value of pull-up cannot be programmed.
Rev. 0
|
Page 13 of 48
|
June 2007
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