參數(shù)資料
型號(hào)： ADSP-21371BSWZ-2B
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/48頁(yè)
文件大?。?/td> 0K
描述： IC DSP 32BIT 266MHZ 208-LQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： DAI，DPI
時(shí)鐘速率： 266MHz
非易失內(nèi)存： ROM（512 kB）
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 208-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 208-LQFP-EP（28x28）
包裝： 托盤
ADSP-21371
Note the definitions of various clock periods shown in Table 12
which are a function of CLKIN and the appropriate ratio con
trol shown in Table 11.
Table 11. ADSP-21371 CLKOUT and CCLK Clock
Generation Operation
Timing
Requirements
CLKIN
CCLK
Description
Input Clock
Core Clock
Calculation
1/tCK
1/tCCLK
Table 12. Clock Periods
Timing
Requirements
Description1
tCK
CLKIN Clock Period
tCCLK
(Processor) Core Clock Period
tPCLK
(Peripheral) Clock Period = 2 × tCCLK
tSCLK
Serial Port Clock Period = (tPCLK) × SR
tSDCLK
SDRAM Clock Period = (tCCLK) × SDR
tSPICLK
SPI Clock Period = (tPCLLK) × SPIR
1 where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV
bits in DIVx register)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register
setting)
SDR=SDRAM-to-Core Clock Ratio (Values determined by bits 20-18 of the
PMCTL register)
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 36 on Page 44 under Test Conditions for voltage refer
ence levels.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Rev. 0
|
Page 18 of 48
|
June 2007
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