參數(shù)資料
型號(hào)： ADSP-21371BSWZ-2B
廠商： Analog Devices Inc
文件頁數(shù)： 22/48頁
文件大?。?/td> 0K
描述： IC DSP 32BIT 266MHZ 208-LQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： DAI，DPI
時(shí)鐘速率： 266MHz
非易失內(nèi)存： ROM（512 kB）
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 208-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 208-LQFP-EP（28x28）
包裝： 托盤
ADSP-21371
Serial Ports
To determine whether communication is possible between two
Serial port signals (SCLK, FS, Data Channel A, Data Channel B)
devices at clock speed n, the following specifications must be
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
confirmed: 1) frame sync delay and frame sync setup and hold,
timing specifications provided below are valid at the
2) data delay and data setup and hold, and 3) SCLK width.
DAI_P20–1 pins.
Table 27. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
1
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
2.5
ns
tHFSE
1
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
2.5
ns
tSDRE
1
Receive Data Setup Before Receive SCLK
2.5
ns
tHDRE
1
Receive Data Hold After SCLK
2.5
ns
tSCLKW
SCLK Width
10
ns
tSCLK
SCLK Period
20
ns
Switching Characteristics
tDFSE
2
FS Delay After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
10.5
ns
tHOFSE
2
FS Hold After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
2
ns
tDDTE
2
Transmit Data Delay After Transmit SCLK
11
ns
tHDTE
2
Transmit Data Hold After Transmit SCLK
2
ns
1 Referenced to sample edge.
2 Referenced to drive edge.
Table 28. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
1
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
tHFSI
1
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
tSDRI
1
Receive Data Setup Before SCLK
tHDRI
1
Receive Data Hold After SCLK
Switching Characteristics
tDFSI
2
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
tHOFSI
2
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
tDFSIR
2
FS Delay After SCLK (Internally Generated FS in Receive Mode)
tHOFSIR
2
FS Hold After SCLK (Internally Generated FS in Receive Mode)
tDDTI
2
Transmit Data Delay After SCLK
tHDTI
2
Transmit Data Hold After SCLK
tSCKLIW
Transmit or Receive SCLK Width
7
2.5
7
2.5
–1.0
0.5tSCLK – 2
4
10.7
3.6
0.5tSCLK + 2
ns
1 Referenced to the sample edge.
2 Referenced to drive edge.
Rev. 0
|
Page 29 of 48
|
June 2007
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