參數(shù)資料
型號: ADSP-21262SKSTZ200
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: SHARC Processor
中文描述: 16-BIT, 66.67 MHz, OTHER DSP, PQFP144
封裝: LEAD FREE, MS-026BFB, LQFP-144
文件頁數(shù): 33/44頁
文件大小: 1295K
代理商: ADSP-21262SKSTZ200
ADSP-21262
Rev. A
|
Page 33 of 44
|
May 2004
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 28
. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the IDP, see the IDP
chapter of the
ADSP-2126x Peripherals Manual
. Note that the
most significant 16 bits of external PDAP data can be provided
through either the parallel port AD[15:0] or the DAI_P[20:5]
pins. The remaining 4 bits can only be sourced through
DAI_P[4:1]. The timing below is valid at the DAI_P[20:1] pins
or at the AD[15:0] pins.
Table 28. Parallel Data Acquisition Port (PDAP)
Parameter
Timing Requirements
t
SPCLKEN
t
HPCLKEN
t
PDSD
t
PDHD
t
PDCLKW
t
PDCLK
Min
Max
Unit
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
1
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
1
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
1
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
1
Clock Width
Clock Period
2.5
2.5
2.5
2.5
7
20
ns
ns
ns
ns
ns
ns
Switching Characteristics
t
PDHLDD
t
PDSTRB
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
PDAP Strobe Pulse Width
2 × t
CCLK
1 × t
CCLK
– 1
ns
ns
1
Source pins of DATA are ADDR[7:0], DATA[7:0], or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
Figure 24. PDAP Timing
DAI_P[20:1]
(PDAP_CLK)
SAMPLE EDGE
t
PDSD
t
PDHD
t
SPCLKEN
t
HPCLKEN
t
PDCLKW
DATA
DAI_P[20:1]
(PDAP_CLKEN)
t
PDSTRB
t
PDHLDD
DAI_P[20:1]
(PDAP_STROBE)
t
PDCLK
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