參數(shù)資料
型號: ADSP-21262SKSTZ200
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: SHARC Processor
中文描述: 16-BIT, 66.67 MHz, OTHER DSP, PQFP144
封裝: LEAD FREE, MS-026BFB, LQFP-144
文件頁數(shù): 32/44頁
文件大?。?/td> 1295K
代理商: ADSP-21262SKSTZ200
Rev. A
|
Page 32 of 44
|
May 2004
ADSP-21262
Input Data Port (IDP)
The timing requirements for the IDP are given in
Table 27
. IDP
Signals (SCLK, FS, SDATA) are routed to the DAI_P[20:1] pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P[20:1] pins.
Table 27. Input Data Port
Parameter
Timing Requirements
t
SISFS
t
SIHFS
t
SISD
t
SIHD
t
IDPCLKW
t
IDPCLK
Min
Max
Unit
FS Setup Before SCLK Rising Edge
1
FS Hold After SCLK Rising Edge
1
SData Setup Before SCLK Rising Edge
1
SData Hold After SCLK Rising Edge
1
Clock Width
Clock Period
2.5
2.5
2.5
2.5
7
20
ns
ns
ns
ns
ns
ns
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the Precision Clock Generators (PCG) or SPORTs. PCG's input can be either
CLKIN or any of the DAI pins.
Figure 23. IDP Master Timing
DAI_P[20:1]
(SCLK)
DAI_P[20:1]
(FS)
SAMPLE EDGE
t
SISD
t
SIHD
t
SISFS
t
SIHFS
t
IDPCLKW
DAI_P[20:1]
(SDATA)
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參數(shù)描述
ADSP-21262SKSTZ200 制造商:Analog Devices 功能描述:IC 32-BIT DSP
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